參數(shù)資料
型號: UPD784031YGK-BE9
廠商: NEC Corp.
英文描述: 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 16-/8-bit的單晶片微控制器
文件頁數(shù): 67/88頁
文件大?。?/td> 464K
代理商: UPD784031YGK-BE9
67
μ
PD784031Y
(3) IOE1, IOE2
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Serial clock cycle time
t
CYSK1
Input
V
DD
= +5.0 V
±
10 %
250
ns
(SCK1, SCK2)
500
ns
Output
Internal 16 frequency division
T
ns
Serial clock low-level width
t
WSKL1
Input
V
DD
= +5.0 V
±
10 %
85
ns
(SCK1, SCK2)
210
ns
Output
Internal 16 frequency division
0.5T – 40
ns
Serial clock high-level width
t
WSKH1
Input
V
DD
= +5.0 V
±
10 %
85
ns
(SCK1, SCK2)
210
ns
Output
Internal 16 frequency division
0.5T – 40
ns
SI1, SI2 setup time
(to SCK1, SCK2
)
t
SSSK1
40
ns
SI1, SI2 hold time
(from SCK1, SCK2
)
t
HSSK1
40
ns
SO1, SO2 output delay time
(from SCK1, SCK2
)
t
DSOSK
0
50
ns
SO1, SO2 output hold time
(from SCK1, SCK2
)
t
HSOSK
When transferring data
0.5t
CYSK1
– 40
ns
Remarks 1.
The values shown in the table above are those in the condition of C
L
= 100 pF.
2.
T: serial clock cycle set by the software. The minimum value is 16/f
XX
.
(4) UART, UART2
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASCK clock input cycle time
t
CYASK
V
DD
= +5.0 V
±
10 %
125
ns
250
ns
ASCK clock low-level width
t
WASKL
V
DD
= +5.0 V
±
10 %
52.5
ns
85
ns
ASCK clock high-level width
t
WASKH
V
DD
= +5.0 V
±
10 %
52.5
ns
85
ns
相關PDF資料
PDF描述
UPD784031Y 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
UPD784031YGC-3B9 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
UPD784031YGC-8BT 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
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