參數(shù)資料
型號(hào)： UPD784031YGK-BE9
廠商： NEC Corp.
英文描述： 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 16-/8-bit的單晶片微控制器
文件頁數(shù)： 63/88頁
文件大?。?/td> 464K
代理商： UPD784031YGK-BE9
63
μ
PD784031Y
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= AV
DD
= +2.7 to 5.5 V, V
SS
= AV
SS
= 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Address setup time
t
SAST
V
DD
= +5.0 V
±
10 %
(0.5 + a) T – 15
ns
(0.5 + a) T – 31
ns
ASTB high-level width
t
WSTH
V
DD
= +5.0 V
±
10 %
(0.5 + a) T – 17
ns
(0.5 + a) T – 40
ns
Address hold time (from ASTB
↓
)
t
HSTLA
V
DD
= +5.0 V
±
10 %
0.5T – 24
ns
0.5T – 34
ns
Address hold time (from RD
↑
)
t
HRA
0.5T – 14
ns
Address
→
RD
↓
delay time
t
DAR
V
DD
= +5.0 V
±
10 %
(1 + a) T – 9
ns
(1 + a) T – 15
ns
Address float time (from RD
↓
)
t
FRA
0
ns
Address
→
data input time
t
DAID
V
DD
= +5.0 V
±
10 %
(2.5 + a + n) T – 37
ns
(2.5 + a + n) T – 52
ns
ASTB
↓
→
data input time
t
DSTID
V
DD
= +5.0 V
±
10 %
(2 + n) T – 40
ns
(2 + n) T – 60
ns
RD
↓
→
data input time
t
DRID
V
DD
= +5.0 V
±
10 %
(1.5 + n) T – 50
ns
(1.5 + n) T – 70
ns
ASTB
↓
→
RD
↓
delay time
t
DSTR
0.5T – 9
ns
Data hold time (from RD
↑
)
t
HRID
0
ns
RD
↑
→
address active time
t
DRA
After program
read
V
DD
= +5.0 V
±
10 %
0.5T – 8
ns
0.5T – 12
ns
After data
read
V
DD
= +5.0 V
±
10 %
1.5T – 8
ns
1.5T – 12
ns
RD
↑
→
ASTB
↑
delay time
t
DRST
0.5T – 17
ns
RD low-level width
t
WRL
V
DD
= +5.0 V
±
10 %
(1.5 + n) T – 30
ns
(1.5 + n) T – 40
ns
Address hold time (from WR
↑
)
t
HWA
0.5T – 14
ns
Address
→
WR
↓
delay time
t
DAW
V
DD
= +5.0 V
±
10 %
(1 + a) T – 5
ns
(1 + a) T – 15
ns
ASTB
↓
→
data output delay time
t
DSTOD
V
DD
= +5.0 V
±
10 %
0.5T + 19
ns
0.5T + 35
ns
WR
↓
→
data output delay time
t
DWOD
0.5T – 11
ns
ASTB
↓
→
WR
↓
output delay time
t
DSTW
0.5T – 9
ns
Remark
T : T
CYK
(system clock cycle time)
a : 1 in address wait, 0 in the other conditions
n : the number of wait (n
≥
0)
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