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參數(shù)資料
| 型號(hào)： | UPD784031YGK-BE9 |
| 廠商： | NEC Corp. |
| 英文描述： | 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 16-/8-bit的單晶片微控制器 |
| 文件頁(yè)數(shù)： | 42/88頁(yè) |
| 文件大?。?/td> | 464K |
| 代理商： | UPD784031YGK-BE9 |
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42
μ
PD784031Y
Table 8-2. Interrupt Sources
Type
Default
Priority
–
Source
Internal/
External
–
Macro Service
Name
Trigger
Software
BRK instruction
BRKCS instruction
Operand error
Instruction execution
–
If result of exclusive OR between byte of operand and
byte is not FFH when MOV STBC, #byte, MOV WDM,
#byte, or LOCATION instruction is executed
Detection of pin input edge
Overflow of watchdog timer
Detection of pin input edge
(TM1/TM1W capture trigger, TM1/TM1W event counter input)
Detection of pin input edge
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of pin input edge
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of pin input edge
(TM0 capture trigger, TM0 event counter input)
Generation of TM0-CR00 match signal
Generation of TM0-CR01 match signal
Generation of TM1-CR10 match signal
(in 8-bit operation mode)
Generation of TM1W-CR10W match signal
(in 16-bit operation mode)
Generation of TM1-CR11 match signal
(in 8-bit operation mode)
Generation of TM1W-CR11W match signal
(in 16-bit operation mode)
Generation of TM2-CR20 match signal
(in 8-bit operation mode)
Generation of TM2W-CR20W match signal
(in 16-bit operation mode)
Generation of TM2-CR21 match signal
(in 8-bit operation mode)
Generation of TM2W-CR21W match signal
(in 16-bit operation mode)
Generation of TM3-CR30 match signal
(in 8-bit operation mode)
Generation of TM3W-CR30W match signal
(in 16-bit operation mode)
Detection of pin input edge
Detection of pin input edge
End of A/D conversion (transfer of ADCR)
Occurrence of ASI0 reception error
End of ASI0 reception or CSI1 transfer
Non-maskable
–
NMI
WDT
INTP0
External
Internal
External
–
Maskable
0 (highest)
√
1
INTP1
2
INTP2
3
INTP3
4
5
6
INTC00
INTC01
INTC10
Internal
√
7
INTC11
8
INTC20
9
INTC21
10
INTC30
11
12
13
14
15
INTP4
INTP5
INTAD
INTSER
INTSR
INTCSI1
INTST
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
External
√
Internal
√
–
√
16
17
18
19
End of ASI0 transfer
End of CSI1 transfer
Occurrence of ASI2 reception error
End of ASI2 reception or CSI2 transfer
–
√
20
End of ASI2 transfer
21 (lowest)
INTSPC
I
2
C bus stop condition interrupt
Remark
ASI: asynchronous serial interface
CSI: clocked serial interface
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