參數(shù)資料
型號(hào): UPD784031YGK-BE9
廠商: NEC Corp.
英文描述: 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 16-/8-bit的單晶片微控制器
文件頁(yè)數(shù): 49/88頁(yè)
文件大?。?/td> 464K
代理商: UPD784031YGK-BE9
49
μ
PD784031Y
9.3 Programmable Wait
The memory space can be divided into eight spaces and wait states can be independently inserted in each of these
spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore,
the efficiency of the entire system does not drop.
In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have
a sufficient address decode time (this function can be set to the entire space).
9.4 Pseudo Static RAM Refresh Function
The following refresh operations can be performed:
Pulse refresh
: A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The
memory spaces is divided into eight spaces, and a refresh pulse can be output from the
REFRQ pin while a specified memory space is accessed. Therefore, the normal memory
access is not kept to wait by the refresh cycle.
Power-down self-refresh: The low level is output to the REFRQ pin in the standby mode to retain the contents of the
pseudo static RAM.
9.5 Bus Hold Function
A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ)
is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a high-
impedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal
active, and releases the bus to the external bus master.
Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot
be used.
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