參數(shù)資料
型號(hào)： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 9/93頁(yè)
文件大?。?/td> 1601K
代理商： TSPC860XRVZQU66D
9
TSPC860 [Preliminary]
2129B–HIREL–12/04
System Bus Signals
The TSPC860 system bus consists of all signals that interface with the external bus.
Many of these signals perform different functions, depending on how the user assigns
them. The following input and output signals are identified by their abbreviation. Each
signal’s pin number can be found in Figure 4 and Figure 5.
Table 1.
Signal Descriptions
Name
Reset
Number
Type
Description
A(0-31)
Hi-Z
See
Figure 2
Bidirectional
Three-state
Address Bus—Provides the address for the current bus cycle. A0 is
the most-significant signal. The bus is output when an internal
master starts a transaction on the external bus. The bus is input
when an external master starts a transaction on the bus.
TSIZ0
REG
Hi-Z
B9
Bidirectional
Three-state
Transfer Size 0—When accessing a slave in the external bus, used
(together with TSIZ1) by the bus master to indicate the number of
operand bytes waiting to be transferred in the current bus cycle.
TSIZ0 is an input when an external master starts a bus transaction.
Register—When an internal master initiates an access to a slave
controlled by the PCMCIA interface, REG is output to indicate which
space in the PCMCIA card is accessed.
TSIZ1
Hi-Z
C9
Bidirectional
Three-state
Transfer Size 1—Used (with TSIZ0) by the bus master to indicate the
number of operand bytes waiting to be transferred in the current bus
cycle. The TSPC860 drives TSIZ1 when it is bus master. TSIZ1 is
input when an external master starts a bus transaction.
RD/WR
Hi-Z
B2
Bidirectional
Three-state
Read/Write—Driven by the bus master to indicate the direction of the
bus’s data transfer. A logic one indicates a read from a slave device
and a logic zero indicates a write to a slave device.
The TSPC860 drives this signal when it is bus master. Input when an
external master initiates a transaction on the bus.
BURST
Hi-Z
F1
Bidirectional
Three-state
Burst Transaction—Driven by the bus master to indicate that the
current initiated transfer is a burst. The TSPC860 drives this signal
when it is bus master. This signal is input when an external master
initiates a transaction on the bus.
BDIP
GPL_B5
See Section
“Signal
States During
Hardware
Reset” on
page 27
D2
Bidirectional
Three-state
Burst Data in Progress—When accessing a slave device in the
external bus, the master on the bus asserts this signal to indicate
that the data beat in front of the current one is the one requested by
the master. BDIP is negated before the expected last data beat of
the burst transfer.
General-Purpose Line B5-Used by the memory controller when
UPMB takes control of the slave access.
TS
Hi-Z
F3
Bidirectional
Active Pull-up
Transfer Start—Asserted by the bus master to indicate the start of a
bus cycle that transfers data to or from a slave device.
Driven by the master only when it has gained the ownership of the
bus. Every master should negate this signal before the bus
relinquish. TS requires the use of an external pull-up resistor.
The TSPC860 samples TS when it is not the external bus master to
allow the memory controller/PCMCIA interface to control the
accessed slave device. It indicates that an external synchronous
master initiated a transaction.
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