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| 型號： | TSPC860XRVZQU66D |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Communication Processor |
| 中文描述： | 綜合通信處理器 |
| 文件頁數(shù)： | 11/93頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | TSPC860XRVZQU66D |
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11
TSPC860 [Preliminary]
2129B–HIREL–12/04
D(0-31)
Hi-Z (Pulled
Low if
RSTCONF
pulled down)
See
Figure 2
Bidirectional
Three-state
Data Bus—This bidirectional three-state bus provides the general-
purpose data path between the TSPC860 and all other devices. The
32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit
transfers. D0 is the MSB of the data bus.
DP0
IRQ3
Hi-Z
V3
Bidirectional
Three-state
Data Parity 0—Provides parity generation and checking for D(0-7) for
transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves sitting on the external bus. Parity generation and
checking is not supported for external masters.
Interrupt Request 3—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of DP0/IRQ3 (if defined as IRQ3) and
CR/IRQ3 (if defined as IRQ3).
DP1
IRQ4
Hi-Z
V5
Bidirectional
Three-state
Data Parity 1—Provides parity generation and checking for D(8-15)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 4—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of this line (if defined as IRQ4) and
KR/IRQ4/SPKROUT (if defined as IRQ4).
DP2
IRQ5
Hi-Z
W4
Bidirectional
Three-state
Data Parity 2—Provides parity generation and checking for D(16-23)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 5—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
DP3
IRQ6
Hi-Z
V4
Bidirectional
Three-state
Data Parity 3—Provides parity generation and checking for D(24-31)
for transfers to a slave device initiated by the TSPC860. The parity
function can be defined independently for each one of the addressed
memory banks (if controlled by the memory controller) and for the
rest of the slaves on the external bus. Parity generation and checking
is not supported for external masters.
Interrupt Request 6—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of this line (if defined as IRQ6) and the
FRZ/IRQ6 (if defined as IRQ6).
BR
Hi-Z
G4
Bidirectional
Bus Request—Asserted low when a possible master is requesting
ownership of the bus. When the TSPC860 is configured to work with
the internal arbiter, this signal is configured as an input. When the
TSPC860 is configured to work with an external arbiter, this signal is
configured as an output and asserted every time a new transaction is
intended to be initiated (no parking on the bus).
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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| TSS2J45 | TOSHIBA SOLID STATE AC RELAY |
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