參數(shù)資料
型號： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁數(shù)： 17/93頁
文件大小： 1601K
代理商： TSPC860XRVZQU66D
17
TSPC860 [Preliminary]
2129B–HIREL–12/04
IP_B5
LWP1
VF1
Hi-Z
J4
Bidirectional
Input Port B 5—The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 1—This output reports the detection of a
data watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The TSPC860 outputs
VF1 with VF0 and VF2 when instruction flow tracking is required.
VFn reports the number of instructions flushed from the instruction
queue in the core.
IP_B6
DSDI
AT0
Hi-Z
K3
Bidirectional
Three-state
Input Port B 6—The TSPC860 senses this input and its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Development Serial Data Input—Data input for the debug port
interface.
Address Type 0—The TSPC860 drives this bidirectional three-state
line when it initiates a transaction on the external bus. If high (1), the
transaction is the CPM. If low (0), the transaction initiator is the CPU.
This signal is not used for transactions initiated by external masters.
IP_B7
PTR
AT3
Hi-Z
H1
Bidirectional
Three-state
Input Port B 7—The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Program Trace—To allow program flow tracking, the TSPC860
asserts this output to indicate an instruction fetch is taking place.
Address Type 3—The TSPC860 drives the bidirectional three-state
signal when it starts a transaction on the external bus. When the
core initiates a transfer, AT3 indicates whether it is a reservation for a
data transfer or a program trace indication for an instruction fetch.
This signal is not used for transactions initiated by external masters.
OP(0-1)
Low
L4, L2
Output
Output Port 0-1—The TSPC860 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
OP2
MODCK1
STS
Hi-Z
L1
Bidirectional
Output Port 2—This output is generated by the TSPC860 as a result
of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The TSPC860 drives this output to indicate
the start of an external bus transfer or of an internal transaction in
show-cycle mode.
OP3
MODCK2
DSDO
Hi-Z
M4
Bidirectional
Output Port 3—This output is generated by the TSPC860 as a result
of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation to
configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug port
interface.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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