參數(shù)資料
型號： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁數(shù)： 20/93頁
文件大?。?/td> 1601K
代理商： TSPC860XRVZQU66D
20
TSPC860 [Preliminary]
2129B–HIREL–12/04
PA[1]
CLK7
TIN4
BRGO4
T19
Bidirectional
General-Purpose I/O Port A Bit 1—Bit 1 of the general-purpose I/O
port A.
CLK7—One of eight clock inputs that can be used to clock SCCs
and SMCs.
TIN4—Timer 4 external clock input.
BRGO4—BRG4 output clock.
PA[0]
CLK8
TOUT4
L1TCLKB
U19
Bidirectional
General-Purpose I/O Port A Bit 0—Bit 0 of the general-purpose I/O
port A.
CLK8—One of eight clock inputs that can be used to clock SCCs
and SMCs.
TOUT4—Timer 4 output.
L1TCLKB—Transmit clock for the serial interface TDM port B.
PB[31]
SPISEL
REJECT1
C17
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 31—Bit 31 of the general-purpose
I/O port B.
SPISEL—SPI slave select input.
REJECT1—SCC1 CAM interface reject pin.
PB[30]
SPICLK
RSTRT2
C19
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 30—Bit 30 of the general-purpose
I/O port B.
SPICLK—SPI output clock when it is configured as a master or SPI
input clock when it is configured as a slave.
RSTRT2—SCC2 serial CAM interface output signal that marks the
start of a frame.
PB[29]
SPIMOSI
E16
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 29—Bit 29 of the general-purpose
I/O port B.
SPIMOSI—SPI output data when it is configured as a master or SPI
input data when it is configured as a slave.
PB[28]
SPIMISO
BRGO4
D19
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 28—Bit 29 of the general-purpose
I/O port B.
SPIMISO—SPI input data when the TSPC860 is a master; SPI
output data when it is a slave.
BRGO4—BRG4 output clock.
PB[27]
I2CSDA
BRGO1
Hi-Z
E19
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 27—Bit 27 of the general-purpose
I/O port B.
I2CSDA—
TWI
serial data pin. Bidirectional; should be configured as
an open-drain output.
BRGO1—BRG1 output clock.
PB[26]
I2CSCL
BRGO2
F19
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 26—Bit 26 of the general-purpose
I/O port B.
I2CSCL—
TWI
serial clock pin. Bidirectional; should be configured
as an open-drain output.
BRGO2—BRG2 output clock.
PB[25]
SMTXD1
J16
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 25—Bit 25 of the general-purpose
I/O port B.
SMTXD1—SMC1 transmit data output.
PB[24]
SMRXD1
J18
Bidirectional
(Optional:
Open-drain)
General-Purpose I/O Port B Bit 24—Bit 24 of the general-purpose
I/O port B.
SMRXD1—SMC1 receive data input.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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