參數(shù)資料
型號(hào)： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 82/93頁(yè)
文件大?。?/td> 1601K
代理商： TSPC860XRVZQU66D
82
TSPC860 [Preliminary]
2129B–HIREL–12/04
Functional Units
Description
The TSPC860 PowerQUICC integrates the Embedded PowerPC Core with high perfor-
mance, low power peripherals to extend the Freescale Data Communications family of
embedded processors even farther into high end communications and networking prod-
ucts.
The TSPC860 PowerQUICC is comprised of three modules which all use the 32-bit
internal bus: the Embedded PowerPC Core, the System Integration Unit (SIU), and the
Communication Processor Module (CPM). The TSPC860 PowerQUICC block diagram
is shown in Figure 1.
Embedded PowerPC
Core
The Embedded PowerPC Core is compliant with the Book 1 specification for the Pow-
erPC architecture. The Embedded PowerPC Core is a fully static design that consists of
two functional blocks; the integer block and the load/store block. It executes all integer
and load/store operations directly on the hardware. The core supports integer opera-
tions on a 32-bit internal data path and 32-bit arithmetic hardware. The core interface to
the internal and external buses is 32 bits. The core uses a two instruction load/store
queue, a four instruction prefetch queue, and a six instruction history buffer. The core
does branch folding and branch prediction with conditional pre-fetch but without condi-
tional execution. The Embedded PowerPC Core can operate on 32-bit external
operands with one bus cycle.
The PowerPC integer block supports 32 × 32-bit fixed point general purpose registers. It
can execute one integer instruction each clock cycle. Each element in the integer block
is clocked only when valid data is present in the data queue ready for operation. This
assures that the power consumption of the device is held to the absolute minimum
required to perform an operation.
The Embedded PowerPC Core is integrated with MMU’s as well as 4 kbyte instruction
and data caches. Each MMU provides a 32 entry, fully associative instruction and data
TLB, with multiple page sizes of: 4 KB, 16 KB, 512 KB, 256 KB and 8 MB. It will support
16 virtual address spaces with 8 protection groups. Three special registers are available
as scratch registers to support software table walk and update.The instruction cache is 4
kilobytes, two-way, set associative with physical addressing. It allows single cycle
access on hit with no added latency for miss. It has four words per line, supporting burst
line fill using Least Recently Used (LRU) replacement. The cache can be locked on a
per line basis for application critical routines.
The data cache is 4 kilobytes, two-way, set associative with physical addressing. It
allows single cycle access on hit with one added clock latency for miss. It has four words
per line, supporting burst line fill using LRU replacement. The cache can be locked on a
per line basis for application critical routines. The data cache can be programmed to
support copy-back or write-through via the MMU. The inhibit mode can be programmed
per MMU page.
The Embedded PowerPC Core with its Instruction and data caches delivers approxi-
mately 52 MIPS at 40 MHz, using Dhrystone 2.1, based on the assumption that it is
issuing one instruction per cycle with a cache hit rate of 94%.
The Embedded PowerPC Core contains a much improved debug interface that provides
superior debug capabilities without causing any degradation in the speed of operation.
This interface supports six watchpoint pins that are used to detect software events.
Internally it has eight comparators, four of which operate on the effective address on the
address bus. The remaining four comparators are split, with two comparators the effec-
tive address on the data bus, and two comparators operating on the data on the data
bus. The Embedded PowerPC Core can compare using =,
≠
, <, > conditions to generate
watchpoints. Each watchpoint can then generate a breakpoint that can be programmed
to trigger in a programmable number of events.
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