參數(shù)資料
型號(hào)： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁(yè)數(shù)： 65/93頁(yè)
文件大小： 1601K
代理商： TSPC860XRVZQU66D
65
TSPC860 [Preliminary]
2129B–HIREL–12/04
Notes:
1. The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2. Where P = 1/CLKOUT. Thus for a 25 MHz CLKO1 rate, P = 40 ns.
3. These specs are valid for IDL mode only.
4. The strobes and T × D on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
Table 19.
Serial Interface AC Electrical Specifications
Number
Characteristic
All Frequencies
Unit
Min
Max
70
L1RCLK, L1TCLK Frequency (DSC = 0)
(1)(3)
–
SYNCCLK/2.5
MHz
71
L1RCLK, L1TCLK Width Low (DSC = 0)
(3)
P+10
ns
71A
L1RCLK, L1TCLK Width High (DSC = 0)
(2)
P+10
–
ns
72
L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time
–
15
ns
73
L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time)
20
–
ns
74
L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time)
35
–
ns
75
L1RSYNC, L1TSYNC Rise/Fall Time
–
15
ns
76
L1RXD Valid to L1CLK Edge (L1RXD Setup Time)
17
–
ns
77
L1CLK Edge to L1RXD Invalid (L1RXD Hold Time)
13
–
ns
78
L1CLK Edge to L1ST(1-4) Valid
(4)
10
45
ns
78A
L1SYNC Valid to L1ST(1-4) Valid
10
45
ns
79
L1CLK Edge to L1ST(1-4) Invalid
10
45
ns
80
L1CLK Edge to L1TXD Valid
10
55
ns
80A
L1TSYNC Valid to L1TXD Valid
(4)
10
55
ns
81
L1CLK Edge to L1TXD High Impedance
0
42
ns
82
L1RCLK, L1TCLK Frequency (DSC = 1)
–
16 or SYNCCLK/2
MHz
83
L1RCLK, L1TCLK Width Low (DSC = 1)
P+10
–
ns
83A
L1RCLK, L1TCLK Width High (DSC = 1)
(2)
P+10
–
ns
84
L1CLK Edge to L1CLKO Valid (DSC = 1)
–
30
ns
85
L1RQ Valid Before Falling Edge of L1TSYNC
(4)
1
–
L1TCLK
86
L1GR Setup Time
(3)
42
–
ns
87
L1GR Hold Time
42
–
ns
88
L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0,
DSC = 0)
–
0
ns
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