參數(shù)資料
型號(hào)： TSPC860XRVZQU66D
廠商： Atmel Corp.
英文描述： Integrated Communication Processor
中文描述： 綜合通信處理器
文件頁數(shù)： 15/93頁
文件大?。?/td> 1601K
代理商： TSPC860XRVZQU66D
15
TSPC860 [Preliminary]
2129B–HIREL–12/04
SRESET
Low
P2
Open-drain
Soft Reset—Asserting this open drain line puts the TSPC860 in soft
reset state.
XTAL
Analog
Driving
P1
Analog
Output
This output is one of the connections to an external crystal for the
internal oscillator circuitry.
EXTAL
Hi-Z
N1
Analog Input
(3.3V only)
This line is one of the connections to an external crystal for the
internal oscillator circuitry.
XFC
Analog
Driving
T2
Analog Input
External Filter Capacitance—This input is the connection pin for an
external capacitor filter for the PLL circuitry.
CLKOUT
High until
SPLL locked,
then
oscillating
W3
Output
Clock Out—This output is the clock system frequency.
EXTCLK
Hi-Z
N2
Input (3.3V
only)
External Clock — This input is the external input clock from an
external source.
TEXP
High
N3
Output
Timer Expired—This output reflects the status of PLPRCR[TEXPS].
ALE_A
Low
K2
Output
Address Latch Enable A—This output is asserted when TSPC860
initiates an access to a region under the control of the PCMCIA
interface to socket A.
CE1_A
High
B3
Output
Card Enable 1 Slot A—This output enables even byte transfers when
accesses to PCMCIA Slot A are handled under the control of the
PCMCIA interface.
CE2_A
High
A3
Output
Card Enable 2 Slot A—This output enables odd byte transfers when
accesses to PCMCIA Slot A are handled under the control of the
PCMCIA interface.
WAIT_A
Hi-Z
R3
Input
Wait Slot A—This input, if asserted low, causes a delay in the
completion of a transaction on the PCMCIA controlled Slot A.
WAIT_B
Hi-Z
R4
Input
Wait Slot B—This input, if asserted low, causes a delay in the
completion of a transaction on the PCMCIA controlled Slot B.
IP_A(0-1)
Hi-Z
T5, T4
Input
Input Port A 0-1—The TSPC860 monitors these inputs that are
reflected in the PIPR and PSCR of the PCMCIA interface.
IP_A2
IOIS16_A
Hi-Z
U3
Input
Input Port A 2—The TSPC860 monitors these inputs; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
I/O Device A is 16-Bits Ports Size—The TSPC860 monitors this
input when a transaction under the control of the PCMCIA interface
is initiated to an I/O region in socket A of the PCMCIA space.
IP_A(3-7)
Hi-Z
W2, U4,
U5, T6, T3
Input
Input Port A 3-7—The TSPC860 monitors these inputs; their values
and changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Table 1.
Signal Descriptions (Continued)
Name
Reset
Number
Type
Description
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