
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
Page 1/Register 43: SPR Driver
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
Reserved. Write only zeros to these bits.
D4–D3
R/W
00
00: Right-channel class-D driver output stage gain = 6 dB
01: Right-channel class-D driver output stage gain = 12 dB
10: Right-channel class-D driver output stage gain = 18 dB
11: Right-channel class-D driver output stage gain = 24 dB
D2
R/W
0
0: Right-channel class-D driver is muted.
1: Right-channel class-D driver is not muted.
D1
R/W
0
Reserved. Write only zero to this bit.
D0
R
0
0: Not all programmed gains to right-channel class-D driver have been applied yet.
1: All programmed gains to right-channel class-D driver have been applied.
Page 1/Register 44: HP Driver Control
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D5
R/W
000
Debounce time for the headset short-circuit detection
MCLK/DIV (Page
(1)
3/Register 16) =
Internal Oscillator Source
1-MHz Source
000: Debounce time =
0
s
0
s
001: Debounce time =
8
s
7.8
s
010: Debounce time =
16
s
15.6
s
011: Debounce time =
32
s
31.2
s
100: Debounce time =
64
s
62.4
s
101: Debounce time =
128
s
124.9
s
110: Debounce time =
256
s
250
s
111: Debounce time =
512
s
500
s
Note: These values are based on a nominal oscillator
frequency of 8.2 MHz. Values will scale to the actual
oscillator frequency.
D4–D3
R/W
00
00: Default mode for the DAC
01: DAC performance increased by increasing the current
10: Reserved
11: DAC performance increased further by increasing the current again
D2
R/W
0
0: HPL output driver is programmed as headphone driver.
1: HPL output driver is programmed as lineout driver.
D1
R/W
0
0: HPR output driver is programmed as headphone driver.
1: HPRoutput driver is programmed as lineout driver.
D0
R/W
0
Reserved. Write only zero to this bit.
(1)
The clock used for the debounce has a clock period = debounce duration/8.
Page 1/Register 45: Reserved
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
XXXX XXXX
Reserved. Do not write to these registers.
Page 1/Register 46: MICBIAS
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R/W
0
0: Device software power down is not enabled.
1: Device software power down is enabled.
D6–D4
R/W
000
Reserved. Write only zeros to these bits.
D3
R/W
0
0: Programmed MICBIAS is not powered up if headset detection is enabled but headset is not inserted.
1: Programmed MICBIAS is powered up even if headset is not inserted.
D2
R/W
0
Reserved. Write only zero to this bit.
D1–D0
R/W
00
00: MICBIAS output is powered down.
01: MICBIAS output is powered to 2 V.
10: MICBIAS output is powered to 2.5 V.
11: MICBIAS output is powered to AVDD.
134
REGISTER MAP