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參數(shù)資料
| 型號(hào)： | TSC2117IRGZT |
| 廠(chǎng)商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁(yè)數(shù)： | 181/192頁(yè) |
| 文件大?。?/td> | 2728K |
| 代理商： | TSC2117IRGZT |
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TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
Table 5-41. CODEC CLKIN Clock Dividers
Divider
Bits
NDAC
page 0/register 11, D(6:0)
MDAC
page 0/register 12, D(6:0)
DOSR
page 0/register 13, D(1:0) + page 0/register 14, D(7:0)
NADC
page 0/register 18, D(6:0)
MADC
page 0/register 19, D(6:0)
AOSR
page 0/register 20, D(7:0)
The DAC Modulator is clocked by DAC_MOD_CLK. For proper power-up operation of the DAC Channel,
these clocks must be enabled by configuring the NDAC and MDAC clock dividers ( page 0/register 11, bit
D7 =1 and page 0/register 12, bit D7=1). When the DAC channel is powered down, the device internally
initiates a power-down sequence for proper shut-down. During this shut-down sequence, the NDAC and
MDAC dividers must not be powered down, or else a proper low power shut-down may not take place.
The user can read back the power-status flag at page 0/register 37, bit D7 and page 0/register 37, bit D3.
When both the flags indicate power-down, the MDAC divider may be powered down, followed by the
NDAC divider. Note that when the ADC clock dividers are powered down, the ADC clock is derived from
the DAC clocks.
The ADC modulator is clocked by ADC_MOD_CLK. For proper power-up of the ADC Channel, these
clocks are enabled by the NADC and MADC clock dividers (page 0/register 18, bit D7=1 and page
0/register 19, bit D7=1). When the ADC channel is powered down, the device internally initiates a
power-down sequence for proper shut-down. During this shut-down sequence, the NADC and MADC
dividers must not be powered down, or else a proper low power shut-down may not take place. The user
can read back the power-status flag page 0/register 36, bit D6. When this flag indicates power-down, the
MADC divider may be powered down, followed by NADC divider.
When ADC_CLK (ADC DSP clock) is derived from the NDAC divider output, the NDAC must be kept
powered up till the power-down status flags for ADC do not indicate power-down. When the input to the
AOSR clock divider is derived from DAC_MOD_CLK, then MDAC must be powered up when ADC_fS is
needed ( i.e. when WCLK is generated by TSC2117 or AGC is enabled) and can be powered down only
after the ADC power-down flags indicate power-down status.
In general, all the root clock dividers should be powered down only after the child clock dividers have been
powered down for proper operation.
The TSC2117 also has options for routing some of the internal clocks to the output pins of the device to
be used as general purpose clocks in the system. The feature is shown in Figure 5-59.
APPLICATION INFORMATION
89
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSC2117IRGZT | 制造商:Texas Instruments 功能描述:Touch Screen Controller IC |
| TSC22 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EURO TERMINAL BLOCKS |
| TSC2200 | 制造商:BB 制造商全稱(chēng):BB 功能描述:PDA ANALOG INTERFACE CIRCUIT |
| TSC2200EVM | 功能描述:觸摸傳感器開(kāi)發(fā)工具 Touch Screen Contr Eval Mod RoHS:否 制造商:Cypress Semiconductor 工具用于評(píng)估: 接口類(lèi)型: 工作電壓: 最大工作溫度: |
| TSC2200IPW | 功能描述:觸摸屏轉(zhuǎn)換器和控制器 Prog 4-Wire w/12-Bit 125KHz ADC & Key Ifc RoHS:否 制造商:Microchip Technology 類(lèi)型:Resistive Touch Controllers 輸入類(lèi)型:3 Key 數(shù)據(jù)速率:140 SPS 分辨率:10 bit 接口類(lèi)型:4-Wire, 5-Wire, 8-Wire, I2C, SPI 電源電壓:2.5 V to 5.25 V 電源電流:17 mA 工作溫度:- 40 C to + 85 C 封裝 / 箱體:SSOP-20 |
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