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參數(shù)資料
| 型號： | TSC2117IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 145/192頁 |
| 文件大?。?/td> | 2728K |
| 代理商： | TSC2117IRGZT |
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5.6.4.2 DRC Hysteresis
5.6.4.3 DRC Hold
5.6.4.4 DRC Attack Rate
5.6.4.5 DRC Decay Rate
5.6.4.6 Example Setup for DRC
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
DRC hysteresis is programmable by writing to page 0/register 68, bits D1–D0. These bits can be
programmed to represent values between 0 dB and 3 dB in steps of 1dB. It is a programmable window
around the programmed DRC threshold that must be exceeded for disabled DRC to become enabled, or
enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC
hysteresis is set to 3 dB, then if the gain compression in DRC is inactive, the output of the DAC digital
volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly,
when the gain compression in the DRC is active, the output of the DAC digital volume control must fall
below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature prevents
the rapid activation and de-activation of gain compression in DRC in cases when the output of the DAC
digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By
programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.
The recommended value of DRC hysteresis is 3 dB.
The DRC hold is intended to slow the start of decay for a specified period of time in response to a
decrease in energy level. To minimize audible artifacts, it is recommended to set the DRC hold time to 0
through programming page 0/register 69, bits D6–D3 = 0000.
When the output of the DAC digital volume control exceeds the programmed DRC threshold, the gain
applied in the DAC digital volume control is progressively reduced to avoid the signal from saturating the
channel. This process of reducing the applied gain is called attack. To avoid audible artifacts, the gain is
reduced slowly with a rate equaling the attack rate, programmable via page 0/register 70, bits D7–D4.
Attack rates can be programmed from 4-dB gain change per 1/DAC_fS to 1.2207e–5-dB gain change per
1/DAC_fS.
Attack rates should be programmed such that before the output of the DAC digital volume control can clip,
the input signal should be sufficiently attenuated. High attack rates can cause audible artifacts, and
too-slow attack rates may not be able to prevent the input signal from clipping.
The recommended DRC attack rate value is 1.9531e–4 dB per 1/DAC_fS.
When the DRC detects a reduction in output signal swing beyond the programmed DRC threshold, the
DRC enters a decay state, where the applied gain in the digital-volume control is gradually increased to
programmed values. To avoid audible artifacts, the gain is slowly increased with a rate equal to the decay
rate programmed through page 0/register 70, bits D3–D0. The decay rates can be programmed from
1.5625e–3 dB per 1/DAC_fS to 4.7683e–7 dB per 1/DAC_fS. If the decay rates are programmed too high,
then sudden gain changes can cause audible artifacts. However, if it is programmed too slow, then the
output may be perceived as too low for a long time after the peak signal has passed.
The recommended Value of DRC attack rate is 2.4414e–5 dB per 1/DAC_fS.
PGA Gain = 12 dB
Threshold = –24 dB
Hysteresis = 3 dB
Hold time = 0 ms
Attack Rate = 1.9531e–4 dB per 1/DAC_f
S
Decay Rate = 2.4414e–5 dB per 1/DAC_f
S
APPLICATION INFORMATION
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