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5.9.2
Primary and Secondary Digital Audio Interface Selection
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
SLAS550A – APRIL 2009 – REVISED JUNE 2009
www.ti.com
The audio serial interface on the TSC2117 has extensive IO control to allow communication with two
independent processors for audio data. Each processor can communicate with the device one at a time.
This feature is enabled by register programming of the various pin selections.
Table 5-44 shows the
Primary and Secondary Audio Interface Selection and Registers.
Table 5-45 shows the selection criteria
for generating ADC_WCLK.
Figure 5-72 is a high-level diagram showing the general signal flow and
multiplexing for Primary and Secondary Audio Interfaces. For detail information reference the tables and
register definitions.
Table 5-44. Primary and Secondary Audio Interface Selection
Desired Pin
Possible
Page 0 Registers
Comment
Function
Pins
R27/D2 = 1
Primary WCLK is output from codec
Primary WCLK
WCLK
(OUT)
R33/D5–D4
Select source of Primary WCLK (DAC_fs, ADC_fs, or Secondary WCLK)
Primary WCLK (IN)
WCLK
R27/D2 = 0
Primary WCLK is input to codec
R27/D3 = 1
Primary BCLK is output from codec
Primary BCLK
BCLK
(OUT)
R33/D7
Select source of Primary WCLK (internal BCLK or Secondary BCLK)
Primary BCLK (IN)
BCLK
R27/D3 = 0
Primary BCLK is input to codec
Primary SDIN (IN)
SDIN
R32/D0
Select SDIN to internal interface (0=Primary SDIN; 1=Secondary SDIN)
R53/D3–D1 = 001
SDOUT = primary SDOUT for codec interface
Primary SDOUT
SDOUT
Select source for SDOUT (0 = SDOUT from Interface Block; 1 = secondary
(OUT)
R33/D1
SDIN)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
GPIO1
R51/D5–D2 = 1001
GPIO1 = Secondary WCLK output
R33/D3–D2
Select source of Secondary WCLK (DAC_fs, ADC_fs, or Primary WCLK)
R31/D4–D2 = 010
Secondary WCLK obtained from MISO pin
MISO
R55/D4–D1 = 1010
MISO = Secondary WCLK output
R33/D3–D2
Select source of Secondary WCLK (DAC_fs, ADC_fs, or Primary WCLK)
Secondary WCLK
(OUT)
R31/D4–D2 = 011
Secondary WCLK obtained from SDOUT pin
SDOUT
R53/D3–D1 = 111
SDOUT = Secondary WCLK output
R33/D3–D2
Select source of Secondary WCLK (DAC_fs, ADC_fs, or Primary WCLK)
R31/D4–D2 = 100
Secondary WCLK obtained from GPIO2 pin
GPIO2
R52/D5–D2 = 1001
GPIO2 = Secondary WCLK output
R33/D3–D2
Select source of Secondary WCLK (DAC_fs, ADC_fs, or Primary WCLK)
R31/D4–D2 = 000
Secondary WCLK obtained from GPIO1 pin
GPIO1
R51/D5–D2 = 0001
GPIO1 enabled as Secondary input
R31/D4–D2 = 001
Secondary WCLK obtained from SCLK pin
SCLK
R56/D2–D1 = 11
SCLK enabled as Secondary input
R31/D4–D2 = 100
Secondary WCLK obtained from GPIO2 pin
GPIO2
R52/D5–D2 = 0001
GPIO2 enabled as Secondary input
Secondary WCLK
(IN)
R31/D4–D2 = 101
Secondary WCLK obtained from GPI1 pin
GPI1
R57/D6–D5 = 01
GPI1 enabled as Secondary input
R31/D4–D2 = 110
Secondary WCLK obtained from GPI2 pin
GPI2
R57/D2–D1 = 01
GPI2 enabled as Secondary input
R31/D4–D2 = 111
Secondary WCLK obtained from GPI3 pin
GPI3
R58/D6–D5 = 01
GPI3 enabled as Secondary input
APPLICATION INFORMATION
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