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參數(shù)資料
| 型號： | TSC2117IRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC48 |
| 封裝： | 7 X 7 MM, GREEN, PLASTIC, VQFN-48 |
| 文件頁數(shù)： | 115/192頁 |
| 文件大?。?/td> | 2728K |
| 代理商： | TSC2117IRGZT |
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5.5.2
Automatic Gain Control (AGC)
TSC2117
Low-Power Audio Codec With Embedded miniDSP, Stereo Class-D
Speaker Amplifier, and Smart Four-Wire Touch-Screen Controller
www.ti.com
SLAS550A – APRIL 2009 – REVISED JUNE 2009
The input feed-forward resistance for the MIC input of the microphone PGA stage has three settings of
10 k
, 20 k, and 40 k, which are controlled by writing to page 1/register 48, bits D7 and D6. The input
feed-forward resistance value selected affects the gain of the microphone PGA. The ADC PGA gain for
the MIC input depends on the setting of page1/registers 48 and 49, bits D7–D6. If D7–D6 are set to 01,
then the ADC PGA has 6 dB more gain with respect to the value programmed using page 1/register 47. If
D7–D6 are set to 10, then the ADC PGA has the same gain as programmed using page 1/register 47. If
D7–D6 are set to 11, then the ADC PGA has 6 dB less gain with respect to the value programmed using
page 1/register 47. The same gain scaling is also valid for the AUX1 and AUX2 input, based on the
feed-forward resistance selected using page 1/register 48, bits D5–D2.
The MIC PGA gain can be controlled either by an AGC loop or as a fixed gain. See Figure 1-1 for the
various analog input routings to the MIC PGA that are supported in the single-ended and differential
configurations. The AGC can be enabled by writing to page 0/register 86, bit D7. If the AGC is not
enabled, then setting a fixed gain is done by writing to page 1/register 47, bits D6–D0. Because the
TSC2117 supports soft-stepping gain changes, a read-only flag on page 0/register 36, bit D7 is set
whenever the gain applied by PGA equals the desired value set by the gain register. The MIC PGA can be
enabled by writing to page 1/register 47, bit D7. ADC muting can be done by writing to page 0/register 82,
bit D7 and page 1/register 47, bit D7. Disabling the MIC PGA sets the gain to 0 dB. Muting the ADC
causes the digital output to mute so that the output value remains fixed. When soft-stepping is enabled,
the CODEC_CLKIN signal must stay active until after the ADC power-down register is written, in order to
ensure that soft-stepping to mute has had time to complete. When the ADC POWER UP flag is no longer
set, the CODEC_CLKIN signal can be shut down.
The TSC2117 includes automatic gain control (AGC) for the microphone input (MIC). AGC can be used to
maintain nominally constant output-signal amplitude when recording speech signals. This circuitry
automatically adjusts the MIC PGA gain as the input signal becomes overly loud or very weak, such as
when a person speaking into a microphone moves closer to or farther from the microphone. The AGC
algorithm has several programmable settings, including target gain, attack and decay time constants,
noise threshold, and maximum PGA applicable, that allow the algorithm to be fine-tuned for any particular
application. The algorithm uses the absolute average of the signal (which is the average of the absolute
value of the signal) as a measure of the nominal amplitude of the output signal. Because the gain can be
changed at the sample interval time, the AGC algorithm operates at the ADC_fS clock rate.
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal
level. The TSC2117 allows programming of eight different target levels, which can be programmed from
–5.5 dB to –24 dB relative to a full-scale signal. Because the TSC2117 reacts to the signal absolute
average and not to peak levels, it is recommended that the target level be set with enough margin to avoid
clipping at the occurrence of loud sounds.
An AGC low-pass filter is used to help determine the average level of the input signal. This average level
is compared to the programmed detection levels in the AGC to provide the correct functionality. This
low-pass filter is in the form of a first-order IIR filter. Programming this filter is done by writing to
page 4/registers 2–7. Two 8-bit registers are used to form the 16-bit digital coefficient as shown on the
register map. In this way, a total of six registers are programmed to form the three IIR coefficients.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too
loud. Programming the attack time is done by writing to page 0/register 89, bits D7–D0.
Decay time determines how quickly the PGA gain is increased when the input signal is too low.
Programming the decay time is done by writing to page 0/register 90, bits D7–D0.
APPLICATION INFORMATION
29
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