
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
202
Agere Systems Inc.
11 M13/M23 MUX/DeMUX Registers
(continued)
11.1 M13 Block Register Descriptions
The following tables describe the functions of all bits. For each address, the register bits are indicated as either
read/write (R/W) or read only (RO), and the value of the bits on reset is given.
Table 224. M13_ID_R, M13 Block Identification (RO)
Address
Bit
Table 225. M13_VERSION_R, M13 Version (RO)
Address
Bit
Note:
All bit description in the function column in Table 226 can be found in
Table 236 on page 208.
Table 226. M13_DELTA1, Delta (RO)
Address
Bit
Name
Function
Reset
Default
0x00
0x01
0x10000
15:8
7:0
RSVD
M13_ID[7:0]
Reserved.
The M13_ID_R register returns a fixed value (0x01) when
read.
Name
Function
Reset
Default
0x000
0x0
0x10001
15:3
2:0
RSVD
Reserved.
These bits identify the version number of the M13.
M13_VERSION[2:0]
Name
Function
Reset
Default
0x00
0
0x10004
15:8
7
RSVD
Reserved.
This delta bit is set if M13_RDL_IDLE changes state. It
can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until
another state transition occurs.
This delta bit is set if M13_DS3_LOF changes state. It
can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until
another state transition occurs.
This delta bit is set if M13_DS3_OOF changes state. It
can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until
another state transition occurs.
This delta bit is set if M13_DS3_C1_DET changes state.
It is cleared when read, and it is not set to 1 again until
another state transition occurs.
This delta bit is set if M13_DS3_RAI_DET changes state.
It can be programmed to be either clear on read (COR) or
clear on write (COW), and it is not set to 1 again until
another state transition occurs.
This delta bit is set if M13_DS3_AISPAT_DET changes
state. It can be programmed to be either clear on read
(COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_RDL_IDLED
6
M13_DS3_LOFD
0
5
M13_DS3_OOFD
0
4
M13_DS3_C1_DETD
0
3
M13_DS3_RAI_DETD
0
2
M13_DS3_AISPAT_DETD
0
1
M13_DS3_IDLEPAT_DETD This delta bit is set if M13_DS3_IDLEPAT_DET changes
state. It can be programmed to be either clear on read
(COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
M13_DS3_CBZ_DETD
This delta bit is set if M13_DS3_CBZ_DET changes
state. It can be programmed to be either clear on read
(COR) or clear on write (COW), and it is not set to 1
again until another state transition occurs.
0
0
0