參數(shù)資料
型號: ST52T301P
廠商: 意法半導(dǎo)體
英文描述: 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
中文描述: 8位檢察官辦公室/存儲器DuaLogic]與藝術(shù)發(fā)展局和UART,定時器,可控硅控制器
文件頁數(shù): 44/100頁
文件大?。?/td> 497K
代理商: ST52T301P
9.2SCI TRANSMITTER BLOCK
TheSCI TransmitterBlock consistsof thefollowing
underblocks: SCDR_TX and SHIFT REGISTER,
synchronized, respectively, with the clock master
signal (CKM) and the CLOCK_TX.
The whole block receives through Configuration
Register 3 (M bits) the settings for the following
transmissionmodes (see table9.1):
8-bit word and a singlestop signal
8-bitwordplusaparitybitandasinglestopsignal
8-bit word plusa doublestop signal
9-bit word
In case of 9 bit frame transmission, the most
significative bit arrives through T8 of the
ConfigurationRegister 3.
In an 8-bit transmission, instead, T8 is used to
configure the SCI, according to information
containedinM(seetable9.1):in particularto chose
thepolaritycontrol(evenor odds)toimplementthe
paritycheck.
Aftera RESETsignal, RST, the SCDR_TXblock is
inIDLEstateuntilitreceivesenablingsignal,TE=1,
of ConfigurationRegister 3.
If TE=1, using STX instruction the data, to be
transmitted, are transferred from Register File to
SCDR_TX block and the flag of Input Register 8,
TXEM, is reset to 0, to indicate SCDR_TX block is
full.
If the core supplies a new data, this could not be
loadedinthe SCDR_TXblockuntilthe currentdata
hasnot beenunloadedon theShift Registerblock.
ThismeansthatonlywhenTXEMis 1,itis possible
to load data in the SCDR_TX Block.
Whenthe SHIFT REGISTERBlockloads the data
to be transmitted on an internal buffer, TXEND is
reset to 0 to indicate the beginning of a new
transmission.Atthe end of transmission TXENDis
setto 1, allowing to load in the SHIFT REGISTER
a new data coming from SCDR_TX.
It is important to underline that TXEND = 1 does
notmeanSCDR_TXis readyto receiveanewdata.
Forthisreasonitis bettertoutilisethe TXEMsignal
to synchronize the STX instruction to the SCI
TRANSMITTER block
If ST52x301core resets TE to 0, thetransmission
is interrupted, but the SCI Transmitter block
completes the transmission in progress before to
reset.
9.3 Baud Rate GeneratorBlock
The Baud Rate Generator Block performs the
division of the clock master signal (CKM), in a set
of synchronism frequencies for the serial bit
reception/transmissionon the external line.
Table9.1.showsthe setof frequenciesselectedby
meansof BRSL (ConfigurationRegister 3).
Reception frequency (CLOCK_RX) is 16 times
higherthantransmissionfrequency(CLOCK_TX).
If BRSL is equal to 111, CLOCK_RX and
CLOCK_TX signals coincide with clock master,
CKM.
Figure9.3.SCI Status Input Register
44/99
ST52T301/E301
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