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參數(shù)資料
| 型號： | ST52T301P |
| 廠商： | 意法半導體 |
| 英文描述： | 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER |
| 中文描述： | 8位檢察官辦公室/存儲器DuaLogic]與藝術發(fā)展局和UART，定時器，可控硅控制器 |
| 文件頁數(shù)： | 42/100頁 |
| 文件大?。?/td> | 497K |
| 代理商： | ST52T301P |
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Bit
Name
Value
Description
0
TE
0
Transmission DISABLED
1
Transmission ENABLED
1
RE
0
Receiver DISABLED
1
Receiver ENABLED
2
M
00
8, No Parity,1 bit stop
01
8, No Parity,2 bit stop
3
10
8, Parity,1 bit stop
11
9, No Parity,1 bit stop
4
T8
0
Parity Odd, if Parity is
selected (M
=
10); otherwise
9th Data bit
1
Parity Even, if Parity is
selected (M = 10); otherwise
9th Data bit
5
BRSL
000
600 Hz
001
1200 Hz
010
2400 Hz
6
011
4800 Hz
100
9600 Hz
101
19200 Hz
7
110
38400 Hz
111
External Clock
Table9.1 ConfigurationRegister 3 Setting
theSTARTcondition,theNoiseerrorandtheFrame
error.
When the SCI Receiver is in IDLE status, it is
waiting for the START condition, that is obtained
with a logic level 0, consecutive to a logic level 1.
Thisconditionisdetected,if,withthefixedsampling
time, three logic levels 0 are sampled after three
logic levels 1.
The recognition of the START bit forces the SCI
Receiver Block to enter in an data acquisition
sequence,accordingto serial mode.
The2 bits,M, ofthe ConfigurationRegister3 allow
todefinetheserialmodewiththeconventionshown
in table9.2.
Thebit,T8,incaseof M
=
10
isusedto settheparity
checkto perform,as indicatedin theprevioustable
9.2.
The recognition of STOP condition allows to
transferthe receiveddata,fromRecovery Bufferto
SCDR_RX buffer, adding the eventual ninth data
bit,accordingto themeaningshownintheprevious
table 9.2. After this operation, RXF flag of SCI
StatusInputRegister8 (fig.9.3) is set to logiclevel
1.The ControlUnit readsthe datafromSCDR_RX
buffer (in read-only mode) with SRX instruction
and provides a reset at logic level0 to RDRFflag.
If a data of Recovery Buffer is ready to be
transferredinto SCDR_RXbuffer,but the previous
one was not yet read by the Core, an OVERRUN
Error takesplace:thestatusflag OVERRindicates
the error condition. In this case the information
stored in SCDR_RX buffer is not altered, but the
one that has caused the OVERRUN error can be
overwritten by a new data coming from the serial
dataline.
RecoveryBuffer Block
This block is structured as a synchronised finite
state machine on the CLOCK_RX signal falling
edge.
Whenthe Recovery BufferBlockis in IDLE state it
waits for the reception of the correct 1 and 0
sequencerepresentingthe START.
The recognition takes place by samplingthe input
RxD at CLOCK_RX frequency, that has a
frequency 16 times higher than CLOCK_TX. For
this reason, while the external transmitter sends a
single bit, the Recovery Buffer Block samples 16
states(fromSAMPLE1 to SAMPLE16).
42/99
ST52T301/E301
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