參數(shù)資料
型號(hào)： ST52T301P
廠(chǎng)商： 意法半導(dǎo)體
英文描述： 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
中文描述： 8位檢察官辦公室/存儲(chǔ)器DuaLogic]與藝術(shù)發(fā)展局和UART，定時(shí)器，可控硅控制器
文件頁(yè)數(shù)： 24/100頁(yè)
文件大?。?/td> 497K
代理商： ST52T301P
4.3 Interrupt Sources
ST52x301managesinterruptsignalsgeneratedby
the internal peripherals (Timer, Triac/PWM
Driver,Analog to Digital Converter and Serial
CommunicationPort) or coming from the INT pin.
The polarity of the External Interrupt is
programmedbythe EXTI bit of theREG_CONF14
(see Table 4.1 and fig. 4.4). EXTI=0 means that
INT_EXT is active on rising edge, otherwise it is
activeon fallingedge.
Each peripheral can be programmed in order to
generatethe associateinterrupt;further detailsare
described in the relatedchapter.
4.4 Interrupt Maskability
The interrupts can be masked by configuring the
REG_CONF14.The interrupt is enabledwhen the
bit associated to the mask interrupt is ”1”.
Viceversa, when the bit is ”0”, the interrupt is
maskedand is kept pendent.
For example
LDCF 14, 6
(CONF_REG14 =00000110) enables interrupts
comingfromtheADC(INT_ADC)and fromtheSCI
(INT_SCI).
4.5 Interrupt Priority
Six priority levels are available: level 5 has the
lowestpriority, level 0 has the highestpriority.
Level5 is associatedto the MainProgram,levels4
to 1 are programmable by means of the priority
register called REG_CONF15 (see fig.4.5);
whereas the higher level is related to the external
interrupt (INT_EXT).
Timer, Triac/PWM Driver, SCI and ADC are
identifiedbya two bitsPeripheral Code (see Table
4.2); in order to set the i-th priority level the user
must write the peripherallabel i in the related INTi
priority level.
Bit
Name
Value
Description
0
MSKE
0
External Interrupt
Masked
1
External Interrupt
Not Masked
1
MSKAD
0
A/D Converter Interrupt
Masked
1
A/D Converter Interrupt
Not Masked
2
MSKSCI
0
SCI Interrupt
Masked
1
SCI Interrupt
Not Masked
3
MSKTM
0
TIMER Interrupt
Masked
1
TIMER Interrupt
Not Masked
4
MSKTC
0
TRIAC/ PWM Interrupt
Masked
1
TRIAC/ PWM Interrupt
Not Masked
5
not used
-
6
not used
-
7
EXTI
0
Active on Rising Edge
1
Active on FallingEdge
Table4.1.ConfigurationRegister 14 Description
Name
Description
Priority
Peripheral
Code
Maskable
EPROM
Locations
INT_EXT
External Interrupt (INT)
Ext
Highest
-
yes
200-201
INT_ADC
ADC
Int
Programmable
00
yes
192-193
INT_SCI
SCI
Int
Programmable
01
yes
194-195
INT_TIMER
TIMER
Int
Programmable
10
yes
196-197
INT_TRIAC
TRIAC
Int
Programmable
11
yes
198-199
Table 4.2.InterruptsDescription
24/99
ST52T301/E301
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