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參數(shù)資料
| 型號(hào)： | ST52T301P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER |
| 中文描述： | 8位檢察官辦公室/存儲(chǔ)器DuaLogic]與藝術(shù)發(fā)展局和UART，定時(shí)器，可控硅控制器 |
| 文件頁數(shù)： | 34/100頁 |
| 文件大?。?/td> | 497K |
| 代理商： | ST52T301P |
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D7 D6 D5 D4 D3 D2 D1 D0
REG_CONF6
Timer
TMRST - Internal Timer Reset
TMST
- Internal Timer Start
not used
IESL
TMEL
- Internal/External Signals Selector
- Edge/Level Timer Abilitation
TMS
- Timer Output Shape
POL
- Timer Output Polarity
CKSL
- Internal/External Clock Select
Figure7.6.Timer ConfigurationRegister6
Bit
Name
Value
Description
0
TMRST
0
Stop
1
Start
1
TMST
0
Stop
1
Start
2
IESL
0
Internal Signals
1
External Signals
3
TMEL
0
on Edge
1
on Level
4
CKSL
0
Internal Timer Clock
1
External Timer Clock
5
TMS
0
Pulse Wave(Type 2)
1
Square Wave(Type 1)
6
POL
0
Positive Polarity
1
Negative Polarity
7
not
used
-
Table7.2.ConfigurationRegister 6 Description
CONF_REG6:
TMRST
sets the internalINR signal.
TMST
sets the internalINS signal.
IESL
selects the source of the TRES and
TSTART signals.
IESL=”0”signalsaretheinternalINRand
INS.
IESL=”1” signals come from the TRES
and TCTRL pins.
TMEL
selects the TSTART signal allowing to
workin
LevelMode
orin
EdgeMode
like
previouslydescribed.
TMEL=”0” means EdgeMode
TMEL=”1” means LevelMode.
CKSL
selectsthesourceoftheTMRCLK(work-
ing Timerfrequency).
CKSL=”0”, the TMRCLK is the internal
MCLK divided by the Prescaler starting
value.
CKSL=”1”, the TMRCLK is an external
clock byTCLK pin.
TMS
TIMEROUT is a signal with frequency
equal to the working Timer frequency
dividedby the startingvalue of thePres-
caler (16 bit) and Counter (8 bit). The
Timeroutputcanbe eitherasquarewave
with duty-cycle 50% or a pulse signal
(withthepulsedurationequaltothePres-
caler output signal period).
TMS=”1”, TIMEROUT is a squarewave
TMS=”0”, TIMEROUT is a pulse signal.
POL
defines the polarity of the Timer output
signal (TIMEROUT).
34/99
ST52T301/E301
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