參數(shù)資料
型號(hào)： ST52T301P
廠商： 意法半導(dǎo)體
英文描述： 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
中文描述： 8位檢察官辦公室/存儲(chǔ)器DuaLogic]與藝術(shù)發(fā)展局和UART，定時(shí)器，可控硅控制器
文件頁(yè)數(shù)： 43/100頁(yè)
文件大?。?/td> 497K
代理商： ST52T301P
Bit
Name
Value
Description
0
P8
-
Digital Output Bit
1
ECKF
00
5 MHz
01
10 MHz
2
10
20 MHz
11
20 MHz
3
TXC
0
SCI End Transmission
Interrupt Disabled
1
SCI End Transmission
Interrupt Enabled
4
TDRE
0
SCI TransmissionData
Register Empty Interrupt
Disabled
1
SCI TransmissionData
Register Empty Interrupt
Enabled
5
BRK
0
SCI Break Error Interrupt
Disabled
1
SCI Break Error Interrupt
Enabled
6
OVR
0
SCI Overrun Error Interrupt
Disabled
1
SCI Overrun Error Interrupt
Enabled
7
RDRF
0
SCI Received Data Register
Full Interrupt Disabled
1
SCI Received Data Register
FullInterrupt Enabled
Table9.2 ConfigurationRegister 1 Setting
The analysis of RxD input signal is carried out
lookingthree samples foreach bits received.0
Ifthesethreesamplesarenotequal,thenthenoise
error flag, NSERR, of Input Register 8 is set to 1
and the received data value will be the one
assumedby the majority of the samples.
By means of the procedure described above, to
avoid SCI becomes IDLE, because of a limited
noise due to an erroneous sampling, the
transmissionis recognizedascorrectandthenoise
flag error is set.
At the end of the cycle relative to the reception of
a bit, Recovery Buffer Block will repeat the same
steps 9 times:one step for each received bit, plus
oneforthestopacquisition(10timesincaseof9-bit
data, double stop or parity check).
Attheendof datareception,RecoveryBufferBlock,
will supply informationon eventualframe errorsby
setting to 1 FRERRflag bit of InputRegister 8.
A frameerror can occurif the paritycheckhas not
been successfully achieved or if STOPbit has not
been detected.
If Recovery Buffer Block receives 10 consecutive
bits at logic level 0, a break error occurres, and
interrupt routine request starts.
SCDR_RX block
It is a finite state machine synchronized with the
falling edgeof the clock master signal, CKM.
The SCDR_RX block waits the signal of complete
reception, from the Recovery Buffer, to load the
word received. Moreover, the SCDR_RCX block
loads the values of FRERR and NSERR flag bits
(InputRegister 8), and setsthe RXF flag to 1.
Using SRX instruction the data are transferred to
RegisterFile andRXF flag is resetto 0, toindicate
SCDR_RX blockis empty.
If a new data arrives before the previous one has
been transferred to Register File, an overrunerror
occurres and OVERR flag, of Input Register 8, is
setto 1.
43/99
ST52T301/E301
相關(guān)PDF資料
PDF描述
ST5451D ISDN HDLC AND GCI CONTROLLER
ST5481 L.O.U.I.S - LOW COST USB ISDN SOLUTION
ST5481TQF7 L.O.U.I.S - LOW COST USB ISDN SOLUTION
ST5x86 100 and 120 MHz 3.45 Volt 5x86 CPU(微處理器)
ST62 SERIES 8-Bit OTP/EPROM MCUs with A/D Converter, Oscilator Safeguard, Safe Reset and 20 Pins(8位OTP/EPROM微控制器(8M))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST52T400 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
ST52T400F0B6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
ST52T400F0M6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
ST52T400F1B6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
ST52T400F1M6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT INTELLIGENT CONTROLLER UNIT ICU Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*