參數(shù)資料
型號: ST52T301P
廠商: 意法半導體
英文描述: 8-Bit OTP/EPROM DuaLogic] MCUs WITH ADC, UART, TIMER, TRIAC & PWM DRIVER
中文描述: 8位檢察官辦公室/存儲器DuaLogic]與藝術發(fā)展局和UART,定時器,可控硅控制器
文件頁數(shù): 35/100頁
文件大小: 497K
代理商: ST52T301P
Bit
Name
Value
Description
0
INTSL
0
INT_TMR on Falling Edge of
Counter Stop
1
INT_TMR on Edges of
TIMEROUT
1
INTF
0
NO INT_TMR on Falling
Edge of TIMEROUT
1
INT_TMR on Falling Edge of
TIMEROUT
2
INTR
0
NO INT_TMR on Rising
Edge of TIMEROUT
1
INT_TMR on Rising Edge of
TIMEROUT
3
INPSL
0
Timer Data Input coming
from the Fuzzy Core
1
Timer Data Input coming
from a Register File location
4
FZSL
0
Timer Data Input coming
from FUZZY_OUT_0
1
Timer Data Input coming
from FUZZY_OUT_1
5
not used
-
6
not used
-
7
not used
-
Table7.3.ConfigurationRegister 7 Description
D7 D6 D5 D4 D3 D2 D1 D0
REG_CONF7
Timer
INTSL
INTF
- Interrupt GeneratorSelector
- Interrupton TIMEROUTFallingEdge
INTR
INPSL
FZSL
not used
not used
not used
- Interrupton TIMEROUTRisingEdge
- Input DataSelector
- Fuzzy Input Selector
Figure7.7.Timer ConfigurationRegister7
CONF_REG7:
INTSL
It allows to select the interrupt mode for
the Timer.
INTSL=”0” Interrupt is generated on the
falling edge of the Counter Stop.
INTSL=”1” the interrupt is generated on
the edgesof TIMEROUT.
INTF
INTR
INPSL
selects the source of the value of the
Counterbetweenalocationof theRegis-
ter File and the Fuzzy Core.
INPSL=”0”, Counter value coming from
the FC.
INPSL=”1”, Counter value coming from
the RF.
FZSL=”0”,thevalueoftheTimerCounter
is equalto FUZZY_OUT_0
FZSL=”1”,thevalueoftheTimerCounter
is equalto FUZZY_OUT_1
FZSL
35/99
ST52T301/E301
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