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參數(shù)資料
| 型號(hào)： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SST65P542R |
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Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
2.0 PIN ASSIGNMENTS
FIGURE
2-1: P
IN
A
SSIGNMENTS
FOR
28-
LEAD
SOIC
2.1 Pin Descriptions
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OSC1
OSC2
V
DD
IRQ#
RST#
IRO
V
SS
LPRST#
PC3
PC2
PC1
PC0
PA7
PA6
28-lead SOIC
Top View
368 28-soic ILL P01.5
TABLE
2-1: P
IN
D
ESCRIPTIONS
Symbol
PA[7:0]
Type
I/O
1
Name and Functions
Port A:
The state of any pin in Port A is software programmable and every line is configured as
an input during any reset.
Port B:
The state of any pin in Port B is software programmable and every line is configured as an
input during any reset. Each I/O line contains a programmable interrupt/pull-up for keyscan.
Port C:
Every pin in Port C is a high-current pin and its state is software programmable. All lines
are configured as inputs during any reset.
IRO:
Suitable for driving IR LED biasing logic, the IRO pin is the high-current source and sink out-
put of the carrier modulator transmitter subsystem. Default state is low after any reset.
Low-Power Reset:
An active-low pin, LPRST# function sets MCU to low-power reset mode. Once the
device is in low-power reset mode, it is held in reset with all processor clocks and crystal oscillator halted.
An internal Schmitt trigger is included in the LPRST# pin to improve noise immunity.
Reset:
By setting the RST# pin low, the device is reset to a default state. An internal Schmitt trig-
ger is included in the RST# pin to improve noise immunity.
Oscillator 1,2:
These 2 pins interface with external oscillator circuits. A crystal
resonator, a ceramic resonator, or an external clock signal can be used.
Interrupt Request:
The IRQ# is negative edge-sensitive triggered. An internal Schmitt trigger is
included in the IRQ# pin to improve noise immunity.
Power Supply:
Supply Voltage (2.2-3.2V)
Ground:
Circuit ground. (0V reference)
1. I = Input, O = Output
PB[7:0]
I/O
PC[3:0]
I/O
IRO
O
LPRST#
I
RST#
I
OSC1
OSC2
IRQ#
I
O
I
V
DD
V
SS
PWR
PWR
T2-1.14 368
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