參數(shù)資料
型號(hào)： SST65P542R
廠商： Silicon Storage Technology, Inc.
英文描述： MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
中文描述： 遙控器控制器
文件頁(yè)數(shù)： 25/40頁(yè)
文件大?。?/td> 538K
代理商： SST65P542R
Advance Information
Remote Controller MCU
SST65P542R
25
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
7.0 INTERRUPTS
SST65P542R accepts five sources of interrupts with high-
est to lowest priority: Software Interrupt, External Interrupts
(IRQ# pin / Port B), CMT Interrupt, and Core Timer Inter-
rupt. Whenever multiple interrupt requests are active at the
same time, the higher priority one will be serviced first. All
interrupts are maskable except Software Interrupt which is
generated by executing SWI instruction. To mask inter-
rupts, set the interrupt mask bit of Process Status Word
(PSW). Before serving the interrupt, the MCU registers are
pushed onto the stack in the sequence of PCL, PCH, IDX,
ACC, PSW. The interrupt service routine should clear the
source of interrupt before exiting. By executing RTI instruc-
tion, the stored MCU registers are popped from the stack
and the program resumes from the interrupted location.
7.1 Software Interrupt
The SWI instruction causes MCU to load the contents
of memory locations FFFCH and FFFDH into Program
Counter regardless of the interrupt mask bit in PSW
register.
7.2 External Interrupts
Upon completion of the current instruction, the MCU
responds to the interrupt request that is latched internally.
IRQ# must be asserted (low) for at least one T
ILIH
(125 ns).
Following the completion of the current instruction, the
interrupt latch is tested. If both interrupt mask bit (I bit) in the
PSW is clear and the interrupt request is pending, the inter-
rupt service routine is entered. An external resistor to V
DD
is required by the IRQ# input for wired-AND operation.
The external interrupts, IRQ# pin and Port B interrupts are
edge-sensitive and asserted on the falling edge of the pins.
The Port B Interrupt Control Register enables or disables
interrupts on each individual pin of port B. The External
Interrupt Mask Bit (EIMSK) of Modulator Control and Sta-
tus Register can be used to mask all external interrupts so
that lower priority interrupts such as timer interrupts can be
served. The state of any external interrupt received during
the masked period is preserved. When the EIMSK bit is
clear, the pending interrupts activate the MCU interrupt pro-
cessing again. The external interrupt causes MCU to load
the contents of memory locations FFFAH and FFFBH into
Program Counter.
7.3 CMT Interrupt
A CMT interrupt is generated when the end of cycle flag
(EOC) and the end of cycle interrupt enable (EOCIE) bits
are set in the modulator control and status register
(MCSR). This interrupt will vector to the interrupt service
routine located at the address specified by the contents of
memory locations FFF8H and FFF9H.
7.4 Core Timer Interrupt
The core timer is a 14-stage multifunctional ripple timer.
User can select overflow or real-time interrupt by the setting
of the Core Timer Control Status Register. Please see the
timer section for more details. The timer interrupt causes
MCU to load the contents of memory locations FFF6H and
FFF7H into Program Counter.
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