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參數(shù)資料
| 型號： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 28/40頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SST65P542R |
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Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
10.0 POWER SAVING MODES
SST65P542R provides two power saving modes: Stop
mode and Idle mode. These two modes can be entered
through the setting of the Power Saving Control Register.
Refer to Section 3.1 for power saving control register.
10.1 STOP Mode
Writing a logic ’0’ to the STOP bit of the Power Saving Con-
trol Register enters the STOP mode. To achieve the lowest
possible power consumption, the implementation uses
STOP bit to gate off the internal clock. See Figure 10-1 for
illustration of clock arrangement in the STOP mode. Since
there is no clock input, the internal states are maintained
and not changed including I/O registers and RAM memory
except that the core timer counter bits are cleared. The
external IRQ interrupt can brought the device out of the
STOP mode, but all other interrupts are not served until the
device is recovered from STOP mode. There are three
conditions that will recover the device from the STOP
mode: external IRQ#/Port B interrupt (EIMSK=0), RST# or
external reset LPRST#. The STOP bit will be set to 1 when
the device has been brought out of STOP mode. The inter-
rupt mask bit (I bit) will not be affected.
10.2 IDLE Mode
Writing a logic ’0’ to the IDLE bit of the Power Saving Con-
trol Register enters the IDLE mode. In the IDLE mode, the
timer is still running. Any internal or external interrupt will
recover the device from IDLE mode. If both STOP and
IDLE bits are ’0’, then STOP mode takes effect. The IDLE
bit will be set to 1 when the device has been brought out of
the IDLE mode. The interrupt mask bit (I bit) will not be
affected.
FIGURE
10-1: S
TOP
M
ODE
AND
I
DLE
M
ODE
CPU
IDLE
Clock Generator
÷2
CLK
STOP
Peripherals
368 ILL F04.2
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