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參數(shù)資料
| 型號： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SST65P542R |
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Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
Symbol
IROLP
Function
IRO latch control bit. Reading IROLP bit reads the state of the IRO latch. Writing IROLP updates
the IRO latch with the data being written on the negative edge of the internal processor clock
(F
OSC
/2). Writing to CLR1 to update IROLP will also update the primary carrier low data value.
Care should be taken that bits 5-0 of the data to be written to CHR1 or CLR1.
Primary carrier low time data values. The function of these bits is the same as PH[5:0].
PL[5:0]
Symbol
SH[5:0]
Function
Secondary carrier high time data values. When selected, these bits contain the number of input
clocks required to generate the carrier high time periods. When operating in time mode, CHR2
and CLR2 is never selected. When operating in FSK mode, CHR2, CLR2 and CHR1, CLR1 are
alternately selected under control of the modulator. The secondary carrier high and low time
values are undefined on the reset. These bits must be written to nonzero values before the
carrier generator is enabled when operating in FSK mode.
Symbol
SL[5:0]
Function
Secondary carrier low time data values. The function of these bits is the same as SH[5:0].
Carrier Generator Low Data Register1 (CLR1)
Location
0011H
7
6
5
4
3
2
1
0
Reset Value
00UUUUUUb
IROLP
-
PL5
PL4
PL3
PL2
PL1
PL0
Carrier Generator High Data Register2 (CHR2)
Location
0012H
7
6
5
4
3
2
1
0
Reset Value
00UUUUUUb
-
-
SH5
SH4
SH3
SH2
SH1
SH0
Carrier Generator Low Data Register2 (CLR2)
Location
0013H
7
6
5
4
3
2
1
0
Reset Value
00UUUUUUb
-
-
SL5
SL4
SL3
SL2
SL1
SL0
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