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參數(shù)資料
| 型號(hào)： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SST65P542R |
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Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
4.0 PARALLEL INPUT/OUTPUT PORTS
4.1 Port A
Port A consists of eight individual pins driven by one data
register and one direction register to control the usage of
these pins as either inputs or outputs. All Port A pins are set
to Input mode during any Reset. Software must set the
right direction register first before performing any Read or
Write operation. Any Read operation to the port that was
set as output will read back the data from an internal latch
register instead of the I/O pins. For details, please refer to
Section 3.1 Port A data register and Port A data direction
register.
4.2 Port B
Port B pins are similar to Port A pins except that each of the
Port B pins has a programmable interrupt generation
option which can be enabled for any Port B pins. Port B
pins have optional programmable pull-ups. There is a
choice between pull-up strengths which could be selected
by PU0 or PU1. For details, please refer to Section 3.1, Port
B Interrupt Control Register and Port B Pull-up Control
Register.
FIGURE
4-1: P
ORT
B I
NTERRUPT
AND
P
ULL
-U
P
O
PTIONS
4.3 Port C
Port C is a 4-bit bi-directional port (PC3-PC0). Every Port C
pin has high current driving capability. Reset clears the Port
C Data Register and the data direction register, thereby
returning the ports to inputs. For details, please refer to
Section 3.1 Port C data register and Port C data direction
register.
WEAK1
Interrupt
Logic
368 ILL F03.3
.
INPRB7
DDRB7
From all other Port B Pins
WEAK0
PU0
PU1
PB7
V
DD
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