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參數(shù)資料
| 型號(hào)： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SST65P542R |
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10
Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
Symbol
PA[7:0]
Function
Port A data register bit 0 to 7. These bits are for both reading and writing. Write the data to this
register will output data to port A pins when it’s in output mode. If the pins are set to input mode,
only the output data register is updated, port A pins are tri-stated. Reading the data from this
register will read the state of port A pins when set in input mode. If the pins are set to output
mode, it reads the output data register. See Table 3-2 for details. For a detailed explanation of
each parallel I/O port, please refer to Section 4.0, “Parallel Input/Output Ports” on page 20.
Symbol
PB[7:0]
Function
Port B data register bit 0 to 7. These bits are for both reading and writing. Writing data to this
register will output data to port B pins when it’s in output mode. If the pins are set to input mode,
only the output data register is updated, port B pins are tri-stated. Reading the data from this
register will read the state of port B pins when set in input mode. If the pins are set to output
mode, it reads the output data register. See Table 3-2 for details.
Symbol
PC[3:0]
Function
Port C data register bit 0 to 3. These bits are for both reading and writing. Writing data to this
register will output data to port C pins when it’s in output mode. If the pins are set to input mode,
only output data register is updated, port C pins are tri-stated. Reading data from this register will
read the state of port C pins when set in input mode. If the pins are set to output mode, it reads
the output data register. See Table 3-2 for details.
PORT A Data Register (PORTA)
Location
0000H
7
6
5
4
3
2
1
0
Reset Value
00H
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORT B Data Register (PORTB)
Location
0001H
7
6
5
4
3
2
1
0
Reset Value
00H
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORT C Data Register (PORTC)
Location
0003H
7
6
5
4
3
2
1
0
Reset Value
00H
-
-
-
-
DDRC3
DDRC2
DDRC1
DDRC0
TABLE
3-2:
I/O P
IN
F
UNCTIONS
AS
G
ENERAL
P
URPOSE
I/O
Access
Write
Write
DDRA, DDRB, DDRC
0
1
Mode
Input
Output
I/O Pin Functions
Data is written into the output data register.
Data is written into the output data register and
output to the I/O pins.
The state of I/O is read
The output data register is read
Read
Read
0
1
Input
Output
T3-2.0 368
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