
Advance Information
Remote Controller MCU
SST65P542R
23
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
5.2.6 Operation Status Detection - Program Timer
Method
During the Program or Erase operation, the programmer
can use the timer to decide the completion of the operation.
When a Program or Erase operation is started, system set-
up a timer for T
BP
(for Byte-Program), T
SCE
(for Chip-
Erase), and T
SE
(for Sector-Erase) time period. After this
timer time-out, the operation is completed. See Figure 11-
10 for Program Timer flowchart.
5.2.7 Operation Status Detection - RY/BY# Method
During the internal Program or Erase operation, the signal
RY/BY# indicates the status of the operation. When the
internal Program or Erase operation is in progress, the sig-
nal RY/BY# will be driven low. When the internal Program
or Erase operation is completed, the signal RY/BY# will be
driven high. The device is then ready for the next operation.
See Figure 11-10 for the Program Timer flowchart.
5.2.8 Exiting The External Host Programming Mode
To exit the external host programming mode, the external
host must set the RST# pin to high, and the PROG_RST is
reset to high. The device will exit the host programming and
enter the user mode. The MCU starts execution codes out
of the User Memory Space from the reset vector.
5.2.9 Flash Read Protection
To protect the program code from piracy the flash memory
location 3F80H (user memory address FF80H, flash mem-
ory is mapped to C000H through FFFFH, see Figure 3-1)
is evaluated by the internal hardware to determine the read
protect mode state. During this evaluation period, only the
RY/BY# pin is valid and all other pins are blocked. If this
byte is A3H (read protect is active), a Chip-Erase will be
performed by internal hardware before the external host
programming mode is activated. While the Chip-Erase
could take T
SCE
(See Table 11-5) as maximum time, users
may use RY/BY# pin to determine the completion of the
Chip-Erase. If this byte is not A3H (not read protected), all
of the flash memory are visible by using the external host
programming. During the internal Program or Erase opera-
tion, the signal RY/ BY# indicates the status of the opera-
tion. When the internal Program or Erase operation is in
progress, the RY/BY# will be driven low. When the internal
Program or Erase operation is completed, the RY/BY# will
be driven high. The device is then ready for the next opera-
tion. See Figure 11-10 for the Program Timer flowchart.
Note:
After writing A3H to the flash read protection
register, the device needs to continue power-on
prior to finishing the programming function.
The programming function may include the
Program-Verify function.
TABLE
5-3: E
XTERNAL
H
OST
P
ROGRAMMING
M
ODE
P
IN
A
SSIGNMENT
MODE0=0
MODE1=0
Input A8
Input A9
Input A10
Input A11
Input A12
Input A13
MODE0=0
MODE1=1
Input A0
Input A1
Input A2
Input A3
Input A4
Input A5
Input A6
Input A7
MODE0=1
MODE1=0
Input D0
Input D1
Input D2
Input D3
Input D4
Input D5
Input D6
Input D7
MODE0=1
MODE1=1
Output D0
Output D1
Output D2
Output D3
Output D4
Output D5
Output D6
Output D7
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
T5-3.1 368
TABLE
5-4: S
OFTWARE
C
OMMAND
S
EQUENCE
Command
Sequence
Sector-Erase
Chip-Erase
Byte-Program
1st Bus Write
Cycle
Addr
1
1555H
1555H
1555H
2nd Bus Write
Cycle
Addr
1
2AAAH
2AAAH
2AAAH
3rd Bus Write
Cycle
Addr
1
1555H
1555H
1555H
4th Bus Write
Cycle
Addr
1
1555H
1555H
WA
3
5th Bus Write
Cycle
Addr
1
2AAAH
2AAAH
6th Bus Write
Cycle
Addr
1
SA
X2
1555H
1. Address format A
13
-A
0
(Hex)
2. SA
X
for Sector-Erase; uses A
13
-A
7
address lines
3. WA = Program Byte address
Data
AAH
AAH
AAH
Data
55H
55H
55H
Data
80H
80H
A0H
Data
AAH
AAH
Data
Data
55H
55H
Data
30H
10H
T5-4.3 368