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參數(shù)資料
| 型號： | SST65P542R |
| 廠商： | Silicon Storage Technology, Inc. |
| 英文描述： | MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 遙控器控制器 |
| 文件頁數(shù)： | 22/40頁 |
| 文件大小： | 538K |
| 代理商： | SST65P542R |
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Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
5.2.2 External Host Mode Write Operation
As shown in Figure 11-3, the Write operation needs two
address setup cycles and one data setup cycle. The low to
high transition on SCLK latches the high order address
A[13:8] from the pin AD[5:0] while the MODE[1:0] inputs
are set to 0H; the low to high transition on SCLK latches the
low order address A[7:0] from the pin AD[7:0] while
MODE[1:0] inputs are set to 2H; the low to high transition
on SCLK latches the data D[0:7] from the pin AD[7:0] while
the MODE[1:0] is set to 1H for writing. However, the actual
Write operation to embedded flash memory occurs on the
rising edge of WE#.
5.2.3 External Host Mode Byte-Program Operation
This device is programmed on a byte by byte basis. The
Byte-Program operation consists of three steps. The first
step is the three-byte load sequence for Software Data Pro-
tection. The second step is to load the byte address and
the byte data. The third step is the internal Program opera-
tion which is initiated after the rising edge of the fourth
WE#. The end of the Byte-Program operation can be
determined by using the RY/BY#. Any commands written
during the Byte-Program operation will be ignored. See
Table 5-4 for the software command sequence, Figure 11-5
for the flash Byte-Program timing diagram, and Figure 11-9
for the Byte-Program command sequence flowchart.
5.2.4 External Host Mode Chip-Erase Operation.
The device provides a Chip-Erase operation, which allows
the user to erase the entire memory array to the ’1’s state.
This is useful when the device must be quickly erased
entirely. The Chip-Erase operation is initiated by executing
a six-byte Software Data Protection command sequence,
the last byte Sequence is the address 1555H with the Chip-
Erase command 10H. The Chip-Erase operation begins
with of the sixth write enable’s (WE#) rising edge. The end
of the Chip-Erase can be determined by using the signal
RY/BY#. Any commands written during the Chip-Erase
operation will be ignored. See Table 5-4 for the software
command sequence, Figure 11-4 for the flash Chip-Erase
timing diagram, and Figure 11-11 for the Chip-Erase com-
mand sequence flowchart.
5.2.5 External Host Mode Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 128 Bytes. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence for Software Data Protection, the last byte
sequence is the sector address SA with the Sector-Erase
command 30H. The address lines A[13:7] will be used to
determine the sector address. The internal Erase operation
begins after the sixth write enable’s (WE#) rising edge. The
End-of-Erase can be determined by using the signal RY/
BY#. Any commands written during the Sector-Erase oper-
ation will be ignored. See Table 5-4 for the software com-
mand sequence, Figure 11-5 for the flash Sector-Erase
timing diagram, and Figure 11-11 for the Sector-Erase
command sequence flowchart.
TABLE
5-2: E
XTERNAL
H
OST
P
ROGRAMMING
M
ODE
P
IN
D
ESCRIPTIONS
Pins
8-1
10,20
11
9
13
12
17
18
21
19
23
22
26
Symbol
AD[7:0]
MODE[1:0]
SLCK
PROG_RST
POROUT#
RY/BY#
WE#
OE#
LPRST#
TDIN
TCLKIN
V
SS
V
DD
Type
1
I/O
1
I
I
I
O
O
I
I
I
I
I
PWR
PWR
1. I = Input; O = Output
Name and Functions
Embedded flash memory address and data bus multiplex on AD[7:0] by selecting MODE[1:0]
Address and data bus selection bits in the external host programming mode
Clock for latch address and data after entering the external host programming mode
Reset signal for the external host programming mode
Embedded flash memory power-on reset output
Embedded flash Ready/Busy output. High is ready
Write Enable: embedded flash memory data write enable, low active
Output Enable: embedded flash memory data out enable, low active
Signal for entering the external host programming mode
Data input for entering the external host programming mode
This clock will latch TDIN for entering the external host programming mode
Ground: Circuit ground (0V reference)
Power Supply: Supply voltage (3.2V)
T5-2.3 368
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