參數(shù)資料
型號： SST65P542R
廠商： Silicon Storage Technology, Inc.
英文描述： MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
中文描述： 遙控器控制器
文件頁數(shù)： 24/40頁
文件大?。?/td> 538K
代理商： SST65P542R
24
Advance Information
Remote Controller MCU
SST65P542R
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
6.0 RESET
The 65P542R can be reset from five sources: two external inputs and three internal restart conditions.
FIGURE
6-1: R
ESET
B
LOCK
D
IAGRAM
6.1 External Reset
A low-level input on the RST# pin causes the program
counter to be set to the contents of location FFFEH and
FFFFH (Reset Vector). The MCU is initialized to a known
state. Stack pointer will be reset to FFH. Hardware Reset
is the highest priority input to the chip. An internal Schmitt
trigger is implemented on the RST# input to enhance the
noise immunity.
6.2 External Low Power Reset
The LPRST# is one of the two external sources of a reset.
The signal LPRST# allows the MCU to go into low power
reset mode. All clocks and oscillator to the processor are
halted when the LPRST# is held low. After the LPRST# is
de-asserted (driven high), a delay of 4064 bus clock cycles
is automatically enabled to wait for stable crystal oscillation.
This pin also implements an internal Schmitt trigger to
enhance the noise immunity.
6.3 Internal Power-on and Brown-out
Reset
The internal reset signal will reset the CPU and all
peripheral components. Please refer to Figure 6-1. When
the device is powered up, the internal power-up voltage is
2.0-2.2V. In addition, the internal brown-out voltage is set
to 1.9-2.1V. If the voltage is below the threshold values,
the device will reset in order to protect against the inad-
vertent Write to the flash memory.
6.4 COP Watchdog Timer Reset
SST65P542R has a COP (Computer Operating Properly)
watchdog timer for monitoring the proper operations of
MCU. In normal operation, clearing the COP watchdog
timer is executed by software within a preset period of time
to avoid reaching time-out condition. To clear the COP
watchdog timer, software write “0” to location 3FF0H. The
COP Watchdog Reset is asserted and resets the MCU
when the time-out condition occurs. The COP watchdog
timer is disabled during any external reset. To enable CWT,
write logical “0” to CWT control register (000DH). Refer to
the
SST65P542R Programming User’s Manual
for more
information.
6.5 Illegal Address Reset
An illegal address reset is generated when the MCU
attempts to fetch an instruction from I/O address space
(0000H to 001FH). Those addresses are reserved for I/O
registers only.
368 ILL F16.2
OSC
Data
Address
RST#
LPRST#
Illegal
Address
Reset
4064 Bus
Clock Cycle
Delay
COP
Watchdog
Reset
Reset
Control
Internal
Reset
Address
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