參數(shù)資料
型號(hào)： SST65P542R
廠商： Silicon Storage Technology, Inc.
英文描述： MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
中文描述： 遙控器控制器
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 538K
代理商： SST65P542R
Advance Information
Remote Controller MCU
SST65P542R
13
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
Symbol
CTOF
Function
Core timer overflow bit. CTOF is a real-only status bit, this bit is set when the 8-bit ripple counter
rolls over from FFH to 00H. Writing to this bit has not effect. Reset clears CTOF. CTOF set to
zero by writing a one to TOFC.
Real-time Interrupt bit. RTIF is a read-only status bit. Writing has no effect on this bit. Reset
clears RTIF. The real time interrupt circuit consists of a divider and a one-of-four selector. The
input clock frequency that drives the RTI circuit is E/2
12
with three additional divider stages that
allows a maximum interrupt period of 16 ms at the internal peripheral clock rate of 2.048 MHz.
0: Writing a one to RTFC clears the RTIF.
1: When the output of the chosen (one-of-four selector) stage goes active.
Timer overflow enable bit. TOFE is statuses bit for both read and write. Reset clears this bit.
0: If the CTOF is not set or no timer overflow occurs.
1: If the CTOF is set and a CPU interrupt request is generated
Real time interrupt enable bit. RTIE is a status bit for both read and write. Reset clears this bit.
0: If the RTIF is not set.
1: If the RTIF is set and a CPU interrupt request is generated.
Timer overflow flag clear bit. This bit is for writing only.
0: Writing a zero has no effect on the CTOF bit. This bit always reads as zero.
1: When a one is written to this bit, CTOF is cleared.
Real time interrupt flag clear bit. This bit is for writing only.
0: Writing a zero has no effect on the RTIF bit. This bit always reads as zero.
1: When a one is written to this bit, RTIF is cleared.
Real time interrupt rate select bit. These two bits select one of four taps from the interrupt logic.
See Table 3-4. Reset sets these two bits, which selects the lowest periodic rate and gives the
maximum. Care should be taken when altering RT0 and RT1 if the timeout period is imminent or
uncertain. The CWT should be cleared before changing RTI taps. If the selected tap is modified
during a cycle in which the counter is switching, an RTIF could be missed or an additional one
could be generated.
RTIF
TOFE
RTIE
TOFC
RTFC
RT[1:0]
Core Timer Control Status Register (CTCSR)
Location
0008H
7
6
5
4
3
2
1
0
Reset Value
03H
CTOF
RTIF
TOFE
RTIE
TOFC
RTFC
RT1
RT0
TABLE
3-4:
RTI
AND
CWT R
ATES
AT
4.096 MH
Z
O
SCILLATOR
, P
RESCALER
=1
RTI Rate
RT1-RT0
00
01
10
11
Minimum
CWT
Rates
(2
15
-2
12
)/E
(2
16
-2
13
)/E
(2
17
-2
14
)/E
(2
18
-2
15
)/E
Maximum
CWT
Rates
(2
15
)/E
(2
16
)/E
(2
17
)/E
(2
18
)/E
2ms
4ms
8ms
16ms
2
12
/E
1
2
13
/E
2
14
/E
2
15
/E
1. E is the internal peripheral clock frequency and E = F
OSC
/2
14ms
28ms
56ms
112ms
16ms
32ms
64ms
128ms
T3-4.2 368
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