參數(shù)資料
型號(hào)： SST65P542R
廠商： Silicon Storage Technology, Inc.
英文描述： MOSFET; Transistor Polarity:N Channel; Continuous Drain Current, Id:15A; On-Resistance, Rds(on):0.01ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No
中文描述： 遙控器控制器
文件頁數(shù)： 15/40頁
文件大小： 538K
代理商： SST65P542R
Advance Information
Remote Controller MCU
SST65P542R
15
2001 Silicon Storage Technology, Inc.
S71170-03-000
12/01 368
Symbol
CWT_EN
Function
COP watchdog timer enable bit.
0: COP watchdog timer is enabled.
1: COP watchdog timer is disabled.
Symbol
CWT_CLR
Function
This bit is for writing only. For detail explanation of COP Watchdog Timer Reset, please refer to
Section 6.4
0: Write zero to this bit will clear COP watchdog timer.
1: Write one to this bit has no effect. Read this bit will always returns one.
Symbol
IROLN
Function
IRO latch control bit. Reading IROLN bit reads the state of the IRO latch. Writing IROLN updates
the IRO latch with the data being written on the negative edge of the internal processor clock
(F
OSC
/2). The IRO latch is clear out of reset. Writing to CHR1 to update IROLN will also update
the primary carrier high data value. In addition, writing to CHR1 to update IROLN will update the
CMT polarity bit. Bit 6 should contain the data of CMTPOL polarity bit.
CMT output polarity bit. This bit controls the polarity of the CMT output (IRO).
0: the CMT output is active high.
1: the CMT output is active low.
Primary carrier high time data values. When selected, these bits contain the number of input
clocks required to generate the carrier high time periods. When operating in timer mode, CHR1
and CLR1 are always selected. When operating in FSK mode, CHR1, CLR1 and CHR2, CLR2
are alternately selected under control of the modulator. The primary carrier high and low time
values are undefined on the reset. These bits must be written to non-zero values that before the
carrier generator is enabled to avoid spurious results.
Bit 0 to Bit 7 of CHR1 can be used for both reading and writing.
Note:
“U” indicates that the bit is unaffected after reset.
CMTPOL
PH[5:0]
COP Watchdog Timer Control Register (CWTC)
Location
000DH
7
6
5
4
3
2
1
0
Reset Value
01H
-
-
-
-
-
-
-
CWT_EN
COP Watchdog Timer Reset Register (CWTR)
Location
3FF0H
7
6
5
4
3
2
1
0
Reset Value
01H
-
-
-
-
-
-
-
CWT_CLR
Carrier Generator High Data Register1 (CHR1)
Location
0010H
7
6
5
4
3
2
1
0
Reset Value
00UUUUUUb
IROLN
CMTPOL
PH5
PH4
PH3
PH2
PH1
PH0
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