參數(shù)資料
型號(hào)： SAA7146A
廠商： NXP Semiconductors N.V.
英文描述： Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述： 多媒體橋梁，高性能潔牙機(jī)和PCI電路SPCI
文件頁(yè)數(shù)： 98/144頁(yè)
文件大?。?/td> 645K
代理商： SAA7146A
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1998 Apr 09
98
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 90
UPLOAD handling for the scaler registers
REGISTER
OFFSET
(HEX)
VIDEO EVENT
DESCRIPTION
Initial setting of Dual
D1 Interface
50
no video event
The ‘initial settings of the Dual D1 interface’ contains all
control bits of the scaler part which do not change during a
cyclic processing of the video path. These control bits must
be initialized at the start of the processing. The different
upload conditions of the video path depend on these control
bits. Changing these bits during the cyclic processing can
cause internal pulse signals which generate video events.
These events may not fit into the sequence for the cyclic
processing.
Vertical Blanking Indicator at VS_A port: the VBI is a
V-pulse which depends on the selected edge of the vertical
blanking interval. The edge is defined by the SYNC_A bits.
The selected mode depends on the accepted sync signals.
This register can be uploaded with this V-pulse.
Vertical Blanking Indicator at VS_B port: the VBI is a
V-pulse which depends on the selected edge of the vertical
blanking interval. The edge is defined by the SIO_B bits.
The selected mode depends on the accepted sync signals.
This register can be uploaded with this V-pulse.
Inactive BRS data path: in write mode the BRS data path is
inactive from the falling edge of VGT at the output of the
BRS which means that target line and target byte are
reached to the start of the next field (V-pulse which triggered
the BRS acquisition). For the read mode this register
contains only initial settings which can not change during
cyclic processing.
Inactive HPS data path between two video windows: the
HPS data path is inactive from the falling edge of the VGT at
the output of the HPS, indicating that target line and target
byte are reached, to the start of the next window
processing. V-pulse at the HPS acquisition input.
Video DATA stream
handling at port D1_A
54
VBI_A
Video DATA stream
handling at port D1_B
54
VBI_B
BRS control register
58
BRS_DONE
HPS control
HPS vertical scale
HPS vertical scale
and gain
Chroma key range
HPS output and
formats
Clip control
HPS, horizontal
prescale
HPS, horizontal
fine-scale
BCS control
5C
60
64
HPS_DONE
74
78
78
68
HPS_LINE_DONE
Inactive HPS data path between two lines: The HPS data
path is inactive from the falling edge of the HGT at the
output of the HPS, indicating that target byte are reached to
the start of the next line processing. Rising edge of the HGT
at the HPS acquisition output.
6C
70
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參數(shù)描述
SAA7146AH 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI
SAA7146AH/V3,557 制造商:NXP Semiconductors 功能描述:
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SAA7146AH-V4.557 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit
SAA7146AHZ 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI
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