參數(shù)資料
型號(hào): SAA7146A
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述: 多媒體橋梁,高性能潔牙機(jī)和PCI電路SPCI
文件頁(yè)數(shù): 49/144頁(yè)
文件大?。?/td> 645K
代理商: SAA7146A
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1998 Apr 09
49
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
114
VF2
12
R
Video FIFO 2 underflow/overflow
: this bit is set when the video FIFO 2
has an overflow/underflow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
Video FIFO 1 overflow
: this bit is set when the video FIFO 1 has an
overflow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
Audio input FIFO 2 underflow
: this bit is set when the audio input
FIFO 2 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 2 overflow
: this bit is set when the audio output
FIFO 2 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio input FIFO 1 underflow
: this bit is set when the audio input
FIFO 1 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 1 overflow
: this bit is set when the audio output
FIFO 1 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
reserved
Vertical Gate
: this bit reflects the vertical gate at the HPS output
Line Qualifier Gate
: this bit reflects the horizontal gate at the HPS
output
Event Counter 5 Status
: this bit is set when the event counter 5
exceeds its threshold. This bit is reset by writing a logic 1 to the ECS bit
in the ISR.
Event Counter 4 Status
: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 2 Status
: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 1 Status
: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
VF1
11
R
AF2_in
10
R
AF2_out
9
R
AF1_in
8
R
AF1_out
7
R
6
5
4
R
R
VGT
LNQG
EC5S
3
R
EC4S
2
R
EC2S
1
R
EC1S
0
R
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
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