參數(shù)資料
型號(hào)： SAA7146A
廠商： NXP Semiconductors N.V.
英文描述： Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述： 多媒體橋梁，高性能潔牙機(jī)和PCI電路SPCI
文件頁(yè)數(shù)： 33/144頁(yè)
文件大?。?/td> 645K
代理商： SAA7146A
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1998 Apr 09
33
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 10
Main control register 1
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
Mask word
FC
M15 to M00
31 to 16
RW
16-bit mask word for bit-selective writes to the control word; when
read these bits always return logic 0
Control word
FC
MRST_N
15
RW
Master Reset Not:
this is the master reset for the SAA7146A. Writing
a logic 0 to this bit will reset the SAA7146A to the same state as after
a power-on reset. When read this bit always returns a logic 0.
reserved: when read this bit always returns a logic 0
Enable Register Program Sequencer Task 1
: if ERPS1 = 1, then
any RPS Task 1 action is enabled. If ERPS1 = 0, then RPS Task 1
action does not fetch any more commands.
Enable Register Program Sequencer Task 0
: if ERPS0 = 1, then
any RPS Task 0 action is enabled. If ERPS0 = 0, then RPS Task 0
action does not fetch any more commands.
Enable DEBI Port pins
: if EDP = 0, all pins of the DEBI port are set
to 3-state. If EDP = 1, then the function of all pins at the DEBI port is
as programmed via the DEBI registers.
Enable Real Time Video Ports pins
: if EVP = 0, all 24 pins of the
real time video interface (DD1 port) are 3-stated. If EVP = 1, then the
function of all pins at the real time video interface (DD1 port) is as
programmed by the scaler register; see Table 66.
Enable Audio Port pins
: if EAP = 0, all 14 pins of the audio interface
port are set to 3-state. If EAP = 1, then the function of all pins at the
audio interface is as programmed in Section 7.16.3.
Enable I
2
C Port pins
: if EI2C = 0, then both pins of the I
2
C-bus
interface port are set to 3-state. If EI2C = 1, then the I
2
C-bus interface
is enabled and will function as programmed in Section 7.17.2.
Transfer Enable bit of the DEBI.
Transfer enable bit of video Channel 1: if set this channel is included
in the internal arbitration scheme. If not set, this channel will be
ignored and no transfer will start using this FIFO.
Transfer Enable bit of video channel 2
Transfer Enable bit of video channel 3
Transfer Enable bit of audio channel 2 out
Transfer Enable bit of audio channel 2 in
Transfer Enable bit of audio channel 1 out
Transfer Enable bit of audio channel 1 in
ERPS1
14
13
RW
ERPS0
12
RW
EDP
11
RW
EVP
10
RW
EAP
9
RW
EI2C
8
RW
TR_E_DEBI
TR_E_1
7
6
RW
RW
TR_E_2
TR_E_3
TR_E_A2_OUT
TR_E_A2_IN
TR_E_A1_OUT
TR_E_A1_IN
5
4
3
2
1
0
RW
RW
RW
RW
RW
RW
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