參數(shù)資料
型號(hào)： SAA7146A
廠商： NXP Semiconductors N.V.
英文描述： Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述： 多媒體橋梁，高性能潔牙機(jī)和PCI電路SPCI
文件頁數(shù)： 120/144頁
文件大小： 645K
代理商： SAA7146A
1998 Apr 09
120
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.5.2
Audio input level monitoring
The audio input level monitoring feature allows the control of audio input levels without additional external hardware, by
comparing the absolute value of the most significant byte of an audio sample to a programmable reference maximum
level. The MAXLEVEL is defined by 7 bits, since serial audio data is transmitted in twos complement and the sign of the
compared byte is not relevant for audio level control. Therefore, MAXLEVEL is programmable from 0 to 127. The twos
complement value
128
is not reachable, but also not functionally needed. The comparison results are stored in the
32-bit level report register with one bit per time slot of TSL1 and TSL2, reporting whether there was a level violation in
that time slot. The comparison runs all the time and the level report register is reset when it is read by software.
Table 106
Level report register
7.16.5.3
WS line controlling
The WSx_CTRL bits define which of the WS lines is output and controlled by which audio interface circuit (A1 or A2).
WSx_SYNC defines the timing of WS signals.
Table 107
Static function control for word select lines
Table 108
Pulse width and position control
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
140
LEVEL_REPORT
31 to 0
R
stores the violation of MAXLEVEL for all 32 TSL records;
reset to 0000H when read.
WSx_CTRL
[1:0]
WS0 FUNCTION
WS1 FUNCTION
WS2 FUNCTION
WS3 FUNCTION
WS4 FUNCTION
00
3-state, input,
rising edge resets
TSL1 pointer
output, controlled
by TSL1
output, controlled
by TSL2
output,
active LOW
3-state
3-state
3-state
3-state, input,
rising edge resets
TSL2 pointer
output, controlled
by TSL1
output, controlled
by TSL2
01
output, controlled
by TSL1
output, controlled
by TSL2
output,
active LOW
output, controlled
by TSL1
output, controlled
by TSL2
output, active LOW output, active LOW output, active LOW
output, controlled
by TSL1
output, controlled
by TSL2
10
11
WSx_SYNC
[1:0]
PULSE FUNCTION
00
I
2
S style: WS goes active one bit clock cycle before MSB of time slot and stays active until LSB, i.e. one
bit clock before MSB of next time slot
WS goes active in sync with MSB and stays active until next MSB, i.e. active in sync with current time
slot
WS goes active one bit clock before MSB and stays active for one bit clock cycle, i.e. negative edge is
in sync with beginning of time slot
SINGER style: WS goes active in sync with MSB and stays active for one bit clock cycle and for two bit
clock cycles in first time slot of the superframe
01
10
11
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