參數(shù)資料
型號(hào)： SAA7146A
廠商： NXP Semiconductors N.V.
英文描述： Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述： 多媒體橋梁，高性能潔牙機(jī)和PCI電路SPCI
文件頁(yè)數(shù)： 23/144頁(yè)
文件大?。?/td> 645K
代理商： SAA7146A
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1998 Apr 09
23
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
28
RW2
2
RW
Specifies the data stream direction of FIFO 2. A logic 0 enables a write
operation to the PCI memory. A logic 1 enables a read operation from the
PCI memory.
endian swapping
of all Dwords passing the FIFO 2:
00 = no swap
01 = two byte swap (3210 to 2301)
10 = four byte swap (3210 to 0123)
11 = reserved
Number of lines per field:
in read mode NumLines defines the number of
lines to be read from system memory. A logic 0 specifies one line. In write
mode this register is not used.
Number of bytes per line:
in read mode this defines the number of bytes
per line to be read from system memory. A logic 0 specifies one byte. In
write mode this register is not used.
PCI base address for odd fields
of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
PCI base address for even fields
of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
protection address
reserved
distance between the start addresses of two consecutive lines of a field
base address of the page table
(see Section 7.2.4)
mapping enable
; this bit enables the MMU
reserved
interrupt limit
; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
protection violation
handling
Specifies the data stream direction of FIFO 3. A logic 0 enables a write
operation to the PCI memory. A logic 1 enables a read operation from the
PCI memory.
endian swapping
of all Dwords passing the FIFO 3:
00 = no swap
01 = two byte swap (3210 to 2301)
10 = four byte swap (3210 to 0123)
11 = reserved
Number of lines per field
: in read mode NumLines defines the number of
lines to be read from system memory. A logic 0 specifies one line. In write
mode it defines the number of qualified lines to be processed by the BRS
per field. This will cut off all the following input-lines at the BRS input.
Number of bytes per line
: in read mode this defines the number of bytes
per line to be read from system memory. A logic 0 specifies 1 byte. In write
mode it defines the number of qualified bytes to be processed by the BRS
per line. This will cut off all the following bytes at the BRS input.
Swap2
1 and 0
RW
2C
NumLines2
27 to 16
RW
NumBytes2
11 to 0
RW
30
BaseOdd3
31 to 0
RW
34
BaseEven3
31 to 0
RW
38
ProtAddr3
Pitch3
Page3
ME3
Limit3
31 to 2
1 and 0
31 to 0
31 to 12
11
10 to 8
7 to 4
RW
RW
RW
RW
RW
3C
40
PV3
RW3
3
2
RW
RW
Swap3
1 and 0
RW
44
NumLines3
27 to 16
RW
NumBytes3
11 to 0
RW
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
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