參數(shù)資料
型號： SAA7146A
廠商： NXP Semiconductors N.V.
英文描述： Multimedia bridge, high performance Scaler and PCI circuit SPCI
中文描述： 多媒體橋梁，高性能潔牙機和PCI電路SPCI
文件頁數(shù)： 53/144頁
文件大?。?/td> 645K
代理商： SAA7146A
1998 Apr 09
53
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 45
Event Counter set 2 Register (EC2R)
Table 46
Event Counter set 1 Source Select Register 1 (EC1SSR)
Table 47
Event Counter set 2 Source Select Register (EC2SSR)
Table 48
Status Bit Addresses (SBA)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
11C
EC5 [9:0]
EC4 [9:0]
EC3 [11:0]
31 to 22
21 to 12
11 to 0
R
R
R
Event Counter Five
: this is the fourth 10-bit counter
Event Counter Four
: this is the third 10-bit counter
Event Counter Three
: this is the second 12-bit counter
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E4
31 to 24
reserved
Event Counter 2 Source
: this 6 bit value addresses one of the status bits
Event Counter 2 Enable
: if this bit is set, event counter 2 is enabled
Event Counter 2 Clear
: writing a logic 1 to this bit will clear event counter 2
Event Counter 1 Source
: this 6 bit value addresses one of the status bits
Event Counter 1 Enable
: if this bit is set event counter 1 is enabled
Event Counter 1 Clear
: writing a logic 1 to this bit will clear event counter 1
Event Counter 0 Source
: this 6 bit value addresses one of the status bits
Event Counter 0 Enable
: if this bit is set event counter 0 is enabled
Event Counter 0 Clear
: writing a logic 1 to this bit will clear event counter 0
ECS2 [5:0] 23 to 18
ECEN2
ECCLR2
ECS1 [5:0] 15 to 10
ECEN1
ECCLR1
ECS0 [5:0]
ECEN0
ECCLR0
RW
RW
RW
RW
RW
RW
RW
RW
RW
17
16
9
8
7 to 2
1
0
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E8
31 to 24
reserved
Event Counter 5 Source
: this 6 bit value addresses one of the status bits
Event Counter 5 Enable
: if this bit is set the event counter 5 is enabled
Event Counter 5 Clear
: writing a logic 1 to this bit will clear event counter 5
Event Counter 4 Source
: this 6 bit value addresses one of the status bits
Event Counter 4 Enable
: if this bit is set event counter 4 is enabled
Event Counter 4 Clear
: writing a logic 1 to this bit will clear event counter 4
Event Counter 3 Source
: this 6 bit value addresses one of the status bits
Event Counter 3 Enable
: if this bit is set event counter 3 is enabled
Event Counter 3 Clear
: writing a logic 1 to this bit will clear event counter 3
ECS5 [5:0] 23 to 18
ECEN5
ECCLR5
ECS4 [5:0] 15 to 10
ECEN4
ECCLR4
ECS3 [5:0]
ECEN3
ECCLR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
17
16
9
8
7 to 2
1
0
ADDRESS
(HEX)
STATUS BIT
EVENTS TO BE COUNTED
00
01
02
03
PPEF
PABO
PPED
RPS_I1
number of PCI Parity errors
number of PCI Access errors
every PCI clock cycle with ‘data’ parity error
number of RPS interrupts Task 1
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