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Publication Number S29PL127H_129H_00
Revision A Amendment 1 Issue Date May 7, 2004
PRELIMINARY
S29PL127H/S29PL129H
for Multi-Chip Products (MCP)
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Read/Write Page Mode Flash Memory
Datasheet
Distinctive Characteristics
ARCHITECTURAL ADVANTAGES
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from
random locations within the page
Dual Chip Enable Inputs (S29PL129 only)
— Each CE# input controls a 64 Mbit address space
Single power supply operation
— Full Voltage range: 2.7 to 3.6 volt read, erase, and
program operations for battery-powered applications
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
executing erase/program functions in another bank
— Zero latency switching from write to read operations
Flexible Bank Architecture
— 4 separate banks, with up to two simultaneous
operations per device
S29PL127H:
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
S29PL129H:
— Bank 1A: 48 Mbit (32 Kw x 96)
— Bank 1B: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank 2B: 48 Mbit (32 Kw x 96)
SecSiTM (Secured Silicon) Sector region
— Up to 128 words accessible through a command
sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
Both top and bottom boot blocks in one device
Manufactured on 130 nm process technology
Data retention: 20-years typical
Cycling Endurance: 1 million cycles per sector
typical
PERFORMANCE CHARACTERISTICS
High Performance
— Page access times as fast as 30 ns
— Random access times as fast as 70 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 15 mA program/erase current
— 1 A typical standby mode current
SOFTWARE FEATURES
Software command-set compatible with JEDEC
42.4 standard
— Backward compatible with Am29F and Am29LV
families
CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
operations in other sectors of same bank
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
WP#/ ACC (Write Protect/Acceleration) input
—At VIL, hardware level protection for the first and last
two 4K word sectors.
—At VIH, allows removal of sector protection
—At VHH, provides accelerated programming in a
factory setting
Persistent Sector Protection
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
— Sectors can be locked and unlocked in-system at VCC
level
Password Sector Protection
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
Package options
— Multi Chip Packages (MCP)