![](http://datasheet.mmic.net.cn/170000/S71PL191HB0BFI100_datasheet_9723326/S71PL191HB0BFI100_88.png)
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S29PL127H/S29PL129H
S29PL127H_129H_00A1 May 7, 2004
Pr el i m i n ary
AC CHARACTERISTICS
OE#
CE1#
(PDL129 only)
Addresses
VCCf
WE#
Data
2AAh
SADD
tGHWL
tAH
tWP
tWC
tAS
tWPH
555h for chip erase
10 for Chip Erase
30h
tDS
tVCS
tCS
tDH
55h
tCH
In
Progress
Complete
tWHWH2
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
tRB
tBUSY
Notes:
1. SADD = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Flash Write
Operation Status”.
2. For PL129H during CE1# transitions the other CE1# pin = VIH.
Figure 18. Chip/Sector Erase Operation Timings