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型號：	S71PL191HB0BFI100
廠商：	SPANSION LLC
元件分類：	存儲器
英文描述：	SPECIALTY MEMORY CIRCUIT, PBGA73
封裝：	9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)：	3/172頁
文件大?。?/td>	4662K
代理商：	S71PL191HB0BFI100

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4S29JL064H

S29JL064HA1 May 7, 2004

Pr el i m i n ary

Table Of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . .8

Table 1. S29JL064H Device Bus Operations ........................... 8

Requirements for Reading Array Data ............................................ 9

Writing Commands/Command Sequences .................................... 9

Accelerated Program Operation ......................................................10

Autoselect Functions ............................................................................10

Simultaneous Read/Write Operations with Zero Latency .......10

Automatic Sleep Mode .......................................................................... 11

RESET#: Hardware Reset Pin ............................................................. 11

Output Disable Mode ........................................................................... 12

Table 2. S29JL064H Sector Architecture ...............................13

Table 3. Bank Address .......................................................16

Autoselect Mode ................................................................................... 16

Sector/Sector Block Protection and Unprotection .................... 17

Table 5. S29JL064H Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ..........................................................17

Write Protect (WP#) ........................................................................... 19

Table 6. WP#/ACC Modes ..................................................19

Temporary Sector Unprotect ........................................................... 19

Figure 1. Temporary Sector Unprotect Operation................... 20

Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 21

SecSi (Secured Silicon) Sector

Flash Memory Region .......................................................................... 22

Figure 3. SecSi Sector Protect Verify ................................... 23

Hardware Data Protection ................................................................ 23

Low VCC Write Inhibit ...................................................................... 23

Write Pulse “Glitch” Protection ...................................................... 24

Logical Inhibit ......................................................................................... 24

Power-Up Write Inhibit ..................................................................... 24

Common Flash Memory Interface (CFI) . . . . . . .24

Command Definitions . . . . . . . . . . . . . . . . . . . . . .28

Reading Array Data .............................................................................28

Reset Command ...................................................................................28

Autoselect Command Sequence ...................................................... 29

Enter SecSi Sector/Exit SecSi Sector

Command Sequence ............................................................................ 29

Byte/Word Program Command Sequence ................................... 29

Unlock Bypass Command Sequence ............................................... 30

Figure 4. Program Operation .............................................. 31

Chip Erase Command Sequence ....................................................... 31

Sector Erase Command Sequence .................................................. 32

Figure 5. Erase Operation .................................................. 33

Erase Suspend/Erase Resume Commands .....................................33

Write Operation Status . . . . . . . . . . . . . . . . . . . . .36

DQ7: Data# Polling .............................................................................. 36

Figure 6. Data# Polling Algorithm ....................................... 37

DQ6: Toggle Bit I .................................................................................. 38

Figure 7. Toggle Bit Algorithm ............................................ 39

DQ2: Toggle Bit II ................................................................................ 39

Reading Toggle Bits DQ6/DQ2 ........................................................40

DQ5: Exceeded Timing Limits ..........................................................40

DQ3: Sector Erase Timer ..................................................................40

Table 8. Write Operation Status ......................................... 41

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 42

Figure 8. Maximum Negative Overshoot Waveform................ 42

Figure 9. Maximum Positive Overshoot Waveform ................. 42

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .42

Wireless (W) Devices ......................................................................... 42

Industrial (I) Devices ............................................................................ 42

VCC Supply Voltages ............................................................................42

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43

CMOS Compatible ............................................................................... 43

Figure 10. ICC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) ................................................. 44

Figure 11. Typical ICC1 vs. Frequency .................................. 44

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 12. Test Setup ....................................................... 45

Key To Switching Waveforms . . . . . . . . . . . . . . . .45

Figure 13. Input Waveforms and Measurement Levels............ 45

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 46

Read-Only Operations ...................................................................... 46

Figure 14. Read Operation Timings...................................... 46

Hardware Reset (RESET#) ................................................................ 47

Figure 15. Reset Timings ................................................... 47

Word/Byte Configuration (BYTE#) ................................................48

Figure 16. BYTE# Timings for Read Operations ..................... 49

Figure 17. BYTE# Timings for Write Operations..................... 49

Erase and Program Operations ........................................................ 50

Figure 18. Program Operation Timings ................................. 51

Figure 19. Accelerated Program Timing Diagram ................... 51

Figure 20. Chip/Sector Erase Operation Timings.................... 52

Figure 21. Back-to-back Read/Write Cycle Timings ................ 53

Figure 22. Data# Polling Timings (During Embedded Algorithms)

Figure 23. Toggle Bit Timings (During Embedded Algorithms) . 54

Figure 24. DQ2 vs. DQ6..................................................... 54

Temporary Sector Unprotect .......................................................... 55

Figure 25. Temporary Sector Unprotect Timing Diagram......... 55

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram ................................................. 56

Alternate CE# Controlled Erase and Program Operations .... 57

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Operation Timings............................................................. 58

Erase And Programming Performance . . . . . . . . 59

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 59

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . .60

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