參數(shù)資料
型號： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機械和熱規(guī)格
文件頁數(shù)： 95/126頁
文件大?。?/td> 1563K
代理商： PXA270
Electrical, Mechanical, and Thermal Specification
6-31
Intel PXA270 Processor
AC Timing Specifications
tflashDOH
MD hold from address valid
0
—
—
clk_mem
—
tflashCD
nCS de-asserted after a read/write to
next nCS or nSDCS asserted
(minimum)
1
MSCx[RRR]*2 +
1
15
clk_mem
—
NOTES:
1. Numbers shown as integer multiples of the CLK_MEM period are ideal. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. On the first data beat of burst transfer, the tflashASW is 3 CLK_MEM periods. On subsequent data beats, the tflashASW is 1
CLK_MEM period.
Figure 6-19. 32-Bit Flash Write Timing
Table 6-18. Flash Memory AC Specification (Sheet 2 of 2)
Symbols
Parameters
MIN
TYP
MAX
Units
1
Notes
command address
data address
0b00
0b00
CMD
DATA
0b0000
0b0000
tflashCD
tflashDSWH
tflashDSWH
tflashWL
tflashWL
tflashCD
tflashDH
tflashDH
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAH
tflashCEH
tflashCES
tflashASW
tflashAS
tflashAS
NOTE: MSC0[RDF0] = 2, MSC0[RRR0] = 2
First Bus Cycle
Second Bus Cycle
CLK_MEM
nCS<0>
MA<25:2>
MA<1:0>
nWE
nOE
RDnWR
MD<31:0>
DQM<3:0>
nADV(nSDCAS)
nCSx or nSDCSx
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