參數(shù)資料
型號(hào)： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機(jī)械和熱規(guī)格
文件頁數(shù)： 49/126頁
文件大?。?/td> 1563K
代理商： PXA270
Electrical, Mechanical, and Thermal Specification
4-29
Intel PXA270 Processor
Pin Listing and Signal Definitions
The address signals are driven low and data signals are pulled low during sleep, standby, deep-
sleep, frequency-change modes, and manual self-refresh. All other memory control signals are in
the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they
are kept there by driving SDCKE low.
4.5
Power-Supply Pins
Table 4-5
summarize the power-supply ball count.
§§
nPOE
GPIO (memory controller drives high)
nPWE
GPIO (memory controller drives high)
NOTE:
This indicates that the GPIO pin, if configured for the alternate function
used by the memory controller during reset, drives the represented
value.
NOTE:
SCLK<3> is only available on PXA270 processor family packages
1. MA pins are driven
2. MD pins are pulled low
Table 4-4. Memory Controller Pin Reset Values (Sheet 2 of 2)
Pin Name
Reset, Sleep, Standby, Deep-Sleep, Frequency
Change, and Manual Self-Refresh Mode Values
Table 4-5. Discrete (13x13 VF-BGA) Power Supply Pin Summary
Name
Number of Package Balls
13x13 mm VF-BGA
Number of Pachage Balls
23x23 mm PBGA
VCC_BATT
1
1
VCC_IO
3
3
VCC_USB
4
4
VCC_LCD
2
2
VCC_MEM
19
16
VCC_BB
1
1
VCC_PLL
1
1
VCC_SRAM
4
4
VCC_CORE
14
20
VCC_USIM
1
1
VSS
6
5
VSS_IO
9
9
VSS_MEM
17
17
VSS_BB
1
1
VSS_PLL
1
1
VSS_CORE
56
56
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