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參數(shù)資料
| 型號： | PXA270 |
| 廠商： | Intel Corp. |
| 英文描述： | Electrical, Mechanical, and Thermal Specification |
| 中文描述： | 電氣，機械和熱規(guī)格 |
| 文件頁數(shù)： | 70/126頁 |
| 文件大?。?/td> | 1563K |
| 代理商： | PXA270 |
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6-6
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
AC Timing Specifications
6.2.5
Sleep Mode Timing
Sleep mode is internally asserted, and it asserts the nRESET_OUT and PWR_EN signals.
Figure 6-5
and
Table 6-6
show the required timing parameters for sleep mode.
Note:
When bit SL_ROD is set in the Power Manager Sleep Configuration register, nRESET_OUT, is
not asserted during GPIO reset. See the “Clocks and Power Manager” chapter in the
Intel
PXA27x Processor Family Developer’s Manual
for register details.
Table 6-5. GPIO Reset Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tA_GPIO<1>
Minimum assert time of GPIO<1>
1
in
13.000-MHz input clock cycles
4
4
—
—
cycles
tDHW_OUT_A
Delay between GPIO<1> asserted and
nRESET_OUT asserted in 13.000-MHz
input clock cycles
6
4
—
8
cycles
tDHW_OUT
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, run or
turbo mode
230
—
—
nsec
tDHW_OUT_F
Delay between nRESET_OUT asserted
and nRESET_OUT de-asserted, during
frequency change sequence
5
—
380
μ
s
tCS0
5
Delay between nRESET_OUT de-
assertion and nCS0 assertion
1000
—
—
ns
NOTES:
1. GPIO<1> is not recognized as a reset source again until configured to do so in software. Software must
check the state of GPIO<1> before configuring as a reset to ensure that no spurious reset is generated. For
details, see the “Clocks and Power Manager” chapter in the
Intel PXA27x Processor Family Developer’s
Manual
.
2. Time is 512*N processor clock cycles plus up to 4 cycles of the 13.000-MHz input clock.
3. Time during the frequency-change sequence depends on the state of the PLL lock detector at the assertion
of GPIO reset. The lock detector has a maximum time of 350 μs plus synchronization.
4. In standby, sleep, and deep-sleep modes, this time is in addition to the wake-up time from the low-power
mode.
5. The tCS0 specification is also applicable to Power-On reset, Hardware reset, Watchdog reset and Deep-
Sleep/Sleep mode exit.
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