參數(shù)資料
型號: PXA270
廠商: Intel Corp.
英文描述: Electrical, Mechanical, and Thermal Specification
中文描述: 電氣,機械和熱規(guī)格
文件頁數(shù): 100/126頁
文件大小: 1563K
代理商: PXA270
6-36
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
AC Timing Specifications
6.4.6
Variable-Latency I/O Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for VLIO memory
interfaces with the memory controller.
Table 6-20
lists the timing-information references for both the read and the write timing diagrams.
Note:
Table 6-20
lists programmable register items. For more information on these items, see the
“Memory Controller” chapter in the
Intel PXA27x Processor Family Developer’s Manual
for
register configurations.
Figure 6-23. 16-bit SRAM Write for 4/2/1 Byte(s) Timing
addr
addr+1
addr
addr
'0'
'0'
'0'
'0' or '1'
Bytes 1:0
Bytes 3:2
Bytes 1:0
Byte 0 OR 1
0b00
0b00
0b01 / 0b10
tsramCD
tsramDSWH
tsramDSWH
tsramDSWH
tsramWL
tsramWL
tsramWL
tsramWL
tsramCD
tsramCD
tsramDH
tsramDH
tsramDSWH
tsramDH
tsramDH
tsramCEH
tsramCES
tsramCEH
tsramCES
tsramCEH
tsramWL
tsramASW
tsramAH
tsramCES
tramAS
tramAS
tramAS
32-bit Write
16-bit Write
8-bit Write
NOTE: MSC1[RDF2]=1, MSC1[RDN]=2, MSC1[RRR2]=2
CLK_MEM
nCS<2>
MA<25:1>
MA<0>
nWE
nOE
RDnWR
MD<15:0>
DQM<1:0>
nADV(nSDCAS)
nCSx or nSDCSx
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