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參數(shù)資料
| 型號： | PXA270 |
| 廠商： | Intel Corp. |
| 英文描述： | Electrical, Mechanical, and Thermal Specification |
| 中文描述： | 電氣，機械和熱規(guī)格 |
| 文件頁數(shù)： | 104/126頁 |
| 文件大?。?/td> | 1563K |
| 代理商： | PXA270 |
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6-40
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
AC Timing Specifications
6.4.7
Expansion-Card Interface Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for CompactFlash*
and PC Card* (expansion card) memory interfaces with the memory controller.
Table 6-21
shows the timing parameters used in the timing diagrams,
Figure 6-26
and
Figure 6-27
.
Note:
Table 6-21
lists programmable register items. See the “Memory Controller” chapter in the
Intel
PXA27x Processor Family Developer’s Manual
for register configurations for more information on
these items.
Table 6-21. Expansion-Card Interface AC Specifications
Symbols
Parameters
MIN
TYP
MAX
Units
Notes
tcdAVCL
Address Valid to CMD Low
2
MCx[SET]
127
CLK_MEM
1,2,3,4
tcdCHAI
CMD High to Address Invalid
0
MCx[HOLD]
63
CLK_MEM
1,2,3,5
tcdDVCL
Write Data Valid to CMD Low
—
1
—
CLK_MEM
1,3
tcdCHWDI
CMD High to Write Data Invalid
—
4
—
CLK_MEM
1,3
tcdDVCH
Read Data Valid to CMD High
2
—
—
CLK_MEM
1,3
tcdCHRDI
CMD High to Read Data Invalid
0
—
—
ns
3
tcdCMD
CMD Assert During Transfers
—
tcdCLPS +
tcdPHCH +
nPWAIT
assertion
—
CLK_MEM
1,3
tcdILCL
nIOIS16 Low to CMD Low
4
—
—
CLK_MEM
1,3
tcdCHIH
CMD High to nIOIS16 High
2
—
—
CLK_MEM
1,3
tcdCLPS
CMD Low to nPWAIT Sample
—
x_ASST_WAIT
—
CLK_MEM
1,3,6,7
tcdPHCH
nPWAIT High to CMD High
—
x_ASST_HOLD
—
CLK_MEM
1,3,6,8
NOTES:
1. All numbers shown are ideal, integer multiples of the CLK_MEM period. Actual numbers vary with pin-to-pin differences in
loading and transition direction (rise or fall).
2. Includes signals MA[25:0], nPREG, and nPSKTSEL.
3. CMD refers to signals nPWE, nPOE, nPIOW, and nPIOR
4. Refer to the
Intel PXA27x Processor Family Developer’s Manual
, Expansion Memory Timing Configuration registers to
change the assertion of CMD using the MCx[SET] bit fields.
5. Refer to the
Intel PXA27x Processor Family Developer’s Manual
, Expansion Memory Timing Configuration registers to
increase the assertion of CMD using the MCx[HOLD] bit fields.
6. Refer to the
Intel PXA27x Processor Family Developer’s Manual
, Expansion Memory Timing Configuration registers to
increase timings. The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card
Interface Command Assertion Code table to see the effect of MCx[ASST].
7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the
Intel
PXA27x Processor Family Developer’s Manual
for the correlation between x_ASST_WAIT and the MCx[ASST] bit field.
8. tcdPHCH equals CLK_MEM * x_ASST_HOLD. Refer to the PC Card Interface Command Assertion Code table in the
Intel
PXA27x Processor Family Developer’s Manual
for the correlation between x_ASST_HOLD and the MCx[ASST] bit field.
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