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參數(shù)資料
| 型號(hào)： | PXA270 |
| 廠商： | Intel Corp. |
| 英文描述： | Electrical, Mechanical, and Thermal Specification |
| 中文描述： | 電氣，機(jī)械和熱規(guī)格 |
| 文件頁(yè)數(shù)： | 47/126頁(yè) |
| 文件大小： | 1563K |
| 代理商： | PXA270 |
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Electrical, Mechanical, and Thermal Specification
4-27
Intel PXA270 Processor
Pin Listing and Signal Definitions
4.3
Signal Types
Table 4-2. Pin Usage and Mapping Notes
Note
Description
[1]
GPIO reset/deep sleep operation:
After any reset is asserted or if the PXA270 processor is in deep sleep mode, these
pins are configured as GPIO inputs by default. The input buffers for these pins are disabled to prevent current drain and
must be enabled prior to use by clearing the
read disable hold
bit, PSSR[RDH]. Until RDH is cleared, each pin is pulled
high (Pu-1), pulled low (Pd-0), or floated (Hi-Z).
[2]
Crystal oscillator pins:
These pins connect the external crystals to the on-chip oscillators and are not affected by either
reset or sleep. For more information, see the “Clocks and Power” chapter in the
Intel PXA27x Processor Family
Developer’s Manual
.
[3]
GPIO sleep operation:
During the transition into sleep mode, the configuration of these pins is determined by the
corresponding GPIO setting. This pin is not driven during sleep if the direction of the pin is selected to be an input. If the
direction of the pin is selected as an output, the value contained in the Power Manager GPIO Sleep-State register
(PGSR0/1/2/3) is driven out onto the pin and held while the PXA270 processor is in sleep mode.
Upon exit from sleep mode, GPIOs that are configured as outputs continue to hold the standby, sleep, or deep-sleep state
until software clears the peripheral control hold bit, PSSR[PH]. Software must clear this bit (by writing 0b1 to it) after the
peripherals have been fully configured, as described in Note[1], but before the process actually uses them.
GPIOs that are configured as inputs immediately after exiting sleep mode cannot be used until PSSR[RDH] is cleared.
[4]
Static memory control pins:
During sleep mode, these pins can be programmed either to drive the value in the Power
Manager GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state,
software must set PCFR[FS]. If FS is not set, these pins function as described in Note[3] during the transition to sleep
mode.
[5]
PCMCIA control pins:
During sleep mode, these pins can be programmed either to drive the value in the Power Manager
GPIO Sleep-State register (PGSR0/1/2/3) or to be placed in a Hi-Z (undriven) state. To select the Hi-Z state, software
must set PCFR[FP]. If FP is not set, these pins function as described in Note[3] during the transition to sleep mode.
[6]
(reserved)
[7]
When the power manager overrides the GPIO alternate function, the Power Manager GPIO Sleep-State registers
(PGSR0/1/2/3) and the PSSR[RDH] bit are ignored. Pullup and pulldown are disabled immediately after the power
manager overrides the GPIO function.
[8]
Output functions during sleep mode
[9]
Pull-up always enabled
[10]
(reserved)
[11]
Pins do not function during sleep mode if the OS timer is active
[12]
Pins must be floated by software during sleep mode (floating does not happen automatically)
[13]
(reserved)
[14]
(reserved)
[15]
The pin is three-stateable (Hi-Z) based on the value of PCFR[FS]. There is no PGSR0/1/2/3 setting associated with the
pin because it is not a GPIO.
[16]
PWR_EN goes high during reset, between the assertion of the reset pin and the de-assertion of internal reset within the
PXA270 processor, after SYS_EN is driven high.
[17]
GPIOs 114 and115:
The alternate function configuration of these pins is ignored when either PUCR[USIM114] or
PUCR[USIM115] bits are set. Setting these bits forces the USIM enable signal onto these GPIOs.
[18]
When software sets the OSCC[PIO_EN] or OSCC[TOUT_EN] bits, then any GPIO alternate function setting applied to
GPIO<9> or GPIO <10> is overridden with the CLK_PIO function on GPIO<9> and CLK_TOUT on GPIO<10>.
[19]
Refer to
Table 4-4
.
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