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參數(shù)資料
| 型號： | PPC405EZ-CSAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EZ Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EZ |
| 文件頁數(shù)： | 8/54頁 |
| 文件大小： | 362K |
| 代理商： | PPC405EZ-CSAFFFTX |
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PPC405EZ – PowerPC 405EZ Embedded Processor
8
AMCC Proprietary
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Power PC 405 Processor Core
The PPC405 core is a fixed-point, 32-bit RISC processor.
Features include:
Five-stage pipeline with single-cycle execution of most instructions, including loads and stores
Separate, configurable 16 KB D- and I-caches, both 2-way set associative
Thirty-two 32-bit general purpose registers (GPRs)
Unaligned load/store support
Hardware multiply/divide
Parity detection and reporting for the instruction cache, data cache, and translation look-aside buffer (TLB)
Double word instruction fetch from cache
Translation of the 4GB logical address space into physical addresses
On-chip memory (OCM) interface
Built-in timer and debug support
Power management
32-bit DCR interface
Internal Buses
The PPC405EZ contains three internal buses: the on-chip peripheral bus (OPB), the processor local bus (PLB),
and the device control register (DCR) bus. High bandwidth devices such as the processor and the DMA core utilize
the PLB. Lower bandwidth I/O interfaces such as communications and timer interfaces utilize the OPB.
OPB
The OPB provides 32-bit address and data interfaces, and operates up to 83MHz. There is a bridge between the
OPB and the PLB.
Features include:
- Pipelined read support
- Dynamic bus sizing
- Single-cycle data transfer between masters and slaves
PLB
The Processor Local Bus (PLB) is a high-performance on-chip bus used to connect PLB-equipped master and
slave devices to the PPC405 CPU. It provides a 64-bit data path with 32-bit addressing and operates at up
to166MHz. There is a bridge between the PLB and the OPB.
Features include:
Overlapping read and write transfers
Decoupled address and data buses
Address pipelining
Late master request abort capability
Hidden (overlapped) bus request/grant protocol
Bus arbitration-locking mechanism
Byte-enable capability allows for unaligned half word transfers and 3-B transfers
Support for 16-, 32-, and 64-B line data transfers
Read word address capability
Sequential burst protocol
Guarded and unguarded memory transfers
DMA buffered, flyby, peripheral-to-memory, memory-to-peripheral, and DMA memory-to-memory operations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE200CZ | Power PC 405GP Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405GP-3BE133C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32BIT 0.25UM 133MHZ 3.3V 456PIN EBGA - Trays |
| PPC405GP-3BE133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:Power PC 405GP Embedded Processor |
| PPC405GP-3BE200C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA Tray |
| PPC405GP-3BE200CZ | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 200MHz 3.3V 456-Pin EBGA T/R |
| PPC405GP-3BE266C | 制造商:AppliedMicro 功能描述:MPU 405GP RISC 32-Bit 0.25um 266MHz 3.3V 456-Pin EBGA Tray |
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